hys64t128020hm-5-a Infineon Technologies Corporation, hys64t128020hm-5-a Datasheet - Page 21

• Manufacturer Part Number: hys64t128020hm-5-a
• Description: 214-pin Micro-dimm-ddr2-sdram Modules
• Manufacturer: Infineon Technologies Corporation

Table 13
Symbol
ODT0-
ODTn
A[9:0],
A10/AP,
A[n:11]
DQ[63:0]
DM[8:0]
DQS[17:0],
DQS[17:0]
V
V
V
SDA
SCL
Data Sheet
DD
REF
DDSPD
,
V
SS
Input/Output Functional Description
I
I
I
I/O
Supply —
Supply —
Supply —
I/O
I
Type
I/O
Polarity Function
Active
High
—
—
Active
High
Cross
point
—
—
Power and ground for the DDR SDRAM input buffers and core logic.
Serial EEPROM positive power supply, wired to a separated power pin at the
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM.
This signal is used to clock data into and out of the SPD EEPROM.
Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the
DDR2 SDRAM mode register.
During a Bank Activate command cycle, defines the row address when sampled
at the crosspoint of the rising edge of CK and falling edge of CK. During a Read
or Write command cycle, defines the column address when sampled at the cross
point of the rising edge of CK and falling edge of CK. In addition to the column
address, AP is used to invoke autoprecharge operation at the end of the burst
read or write cycle. If AP is 1, autoprecharge is selected and BA0-BAn defines
the bank to be precharged. If AP is 0, autoprecharge is disabled. During a
Precharge command cycle, AP is used in conjunction with BA[1:0] to control
which bank(s) to precharge. If AP is 1, all banks will be precharged regardless
of the state of BA0-BAn inputs. If AP is 0, then BA0-BAn are used to define which
bank to precharge.
Data Input/Output pins
The data write masks, associated with one data byte. In Write mode, DM
operates as a byte mask by allowing input data to be written if it is 0 but blocks
the write operation if it is 1. In Read mode, DM lines have no effect.
The data strobes, associated with one data byte, sourced with data transfers. In
Write mode, the data strobe is sourced by the controller and is centered in the
data window. In Read mode the data strobe is sourced by the DDR2 SDRAM
and is sent at the leading edge of the data window. DQS signals are
complements, and timing is relative to the crosspoint of respective DQS and
DQS. If the module is to be operated in single ended strobe mode, all DQS
signals must be tied on the system board to
resistor and DDR2 SDRAM mode registers programmed appropriately.
Reference voltage for the SSTL-18 inputs.
connector which supports from 1.7 Volt to 3.6 Volt.
A resistor must be connected from SDA to to
as a pull-up.
21
Micro-DIMM DDR2 SDRAM Modules
HYS64T128020HM–[3.7/5]–A
V
V
SS
DDSPD
through a 20 ohm to 10 Kohm
Electrical Characteristics
on the motherboard to act
04132004-S0LP-CL4Q
Rev. 1.2, 2005-08