hys64t128020hm-5-a Infineon Technologies Corporation, hys64t128020hm-5-a Datasheet - Page 8

• Manufacturer Part Number: hys64t128020hm-5-a
• Description: 214-pin Micro-dimm-ddr2-sdram Modules
• Manufacturer: Infineon Technologies Corporation

Table 5
Pin or Ball
No.
163
60
56
Address Signals
55
162
46
161
159
52
158
51
50
157
48
155
154
54
47
153
167
Data Sheet
Pin Configuration of MDIMM (cont’d)
Name
RAS
CAS
WE
BA0
BA1
BA2
NC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
A13
NC
Pin
Type
I
I
I
I
I
I
NC
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
NC
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
–
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
–
Function
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
Note: When sampled at the cross point of the rising edge of
Bank Address Bus 1:0
Note: Select internal SDRAM memory bank
Bank Address Bus 2
Note: Greater than 512Mb DDR2 SDRAMS
Not Connected
Note: Less than 1Gb DDR2 SDRAMS
Address Inputs 12:0, Address Input 10/Autoprecharge
Note: During a Bank Activate command cycle, defines the row
Address Input 13
Note: Modules based on 4/ 8 component
Not Connected
Note: Modules based on 16 component
CK,and falling edge of CK, RAS, CAS and WE define the
operation to be executed by the SDRAM.
address when sampled at the crosspoint of the rising edge
of CK and falling edge of CK. During a Read or Write
command cycle, defines the column address when sampled
at the cross point of the rising edge of CK and falling edge of
CK. In addition to the column address, AP is used to invoke
autoprecharge operation at the end of the burst read or write
cycle. If AP is HIGH, autoprecharge is selected and BA[2:0]
defines the bank to be precharged. If AP is LOW,
autoprecharge is disabled. During a Precharge command
cycle, AP is used in conjunction with BA[2:0] to control which
bank(s) to precharge. If AP is HIGH, all banks will be
precharged regardless of the state of BA[2:0] inputs. If AP is
LOW, then BA[2:0] are used to define which bank to
precharge.
8
Micro-DIMM DDR2 SDRAM Modules
Pin Configuration and Block Diagrams
HYS64T128020HM–[3.7/5]–A
04132004-S0LP-CL4Q
Rev. 1.2, 2005-08