gs881z36bgd-333i GSI Technology, gs881z36bgd-333i Datasheet - Page 27
gs881z36bgd-333i
Manufacturer Part Number
gs881z36bgd-333i
Description
9mb Pipelined And Flow Through Synchronous Nbt Sram
Manufacturer
GSI Technology
Datasheet
1.GS881Z36BGD-333I.pdf
(39 pages)
- Current page: 27 of 39
- Download datasheet (2Mb)
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Rev: 1.06 3/2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
TDI
TMS
TCK
·
·
·
·
Test Access Port (TAP) Controller
Bypass Register
Instruction Register
ID Code Register
2
31 30 29
0
JTAG TAP Block Diagram
Boundary Scan Register
·
1
0
Control Signals
27/39
·
·
· · ·
GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)
·
2
1
0
·
·
·
·
TDO
© 2002, GSI Technology
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