saa5547ps NXP Semiconductors, saa5547ps Datasheet - Page 34

• Manufacturer Part Number: saa5547ps
• Description: Saa550x; Saa554x Tv Microcontrollers With Closed Captioning Cc And On-screen Display Osd
• Manufacturer: NXP Semiconductors

Philips Semiconductors
12 TIMER/COUNTER
Two 16-bit timers/counters are incorporated Timer 0 and
Timer 1. Both can be configured to operate as either timers
or event counters.
In Timer mode, the register is incremented on every
machine cycle. It is therefore counting machine cycles.
Since the machine cycle consists of twelve oscillator
periods, the count rate is
In Counter mode, the register is incremented in response
to a negative transition at its corresponding external pin T0
or T1. Since the pins T0 and T1 are sampled once per
machine cycle, it takes two machine cycles to recognise a
transition, this gives a maximum count rate of
1
There are six Special Function Registers used to control
the timers/counters. These are: TCON, TMOD, TL0, TH0,
TL1 and TH1.
The timer/counter function is selected by control bits C/T in
the Timer Mode SFR (TMOD). These two Timer/Counters
have four operating modes, which are selected by bit-pairs
(M1 and M0) in TMOD. Detail of the modes of operation is
given in “Handbook IC20, 80C51-Based 8-bit
Microcontrollers” .
TL0 and TH0 are the actual Timer/Counter registers for
Timer 0. TL0 is the low byte and TH0 is the high byte.
TL1 and TH1 are the actual Timer/Counter registers for
Timer 1. TL1 is the low byte and TH1 is the high byte.
13 WATCHDOG TIMER
The Watchdog Timer is a counter that once in an overflow
state forces the microcontroller into a reset condition.
The purpose of the Watchdog Timer is to reset the
microcontroller if it enters an erroneous processor state
(possibly caused by electrical noise or RFI) within a
reasonable period of time. When enabled, the Watchdog
circuitry will generate a system reset if the user program
fails to reload the Watchdog Timer within a specified length
of time known as the Watchdog Interval (WI).
The Watchdog Timer consists of an 8-bit counter with an
11-bit prescaler. The prescaler is fed with a signal whose
frequency is
2000 Feb 23
24
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
f
osc
= 0.5 MHz.
1
12
f
osc
(1 MHz for 12 MHz oscillator).
1
12
f
osc
= 1 MHz.
34
The 8-bit timer is incremented every ‘t’ seconds where:
13.1
The Watchdog operation is activated when the WLE bit in
the Power Control SFR (PCON) is set. The Watchdog can
be disabled by software by loading the value 55H into the
Watchdog Timer Key SFR (WDTKEY). This must be
performed before entering the Idle or Power-down mode to
prevent exiting the mode prematurely.
Once activated the Watchdog Timer SFR (WDT) must be
reloaded before the timer overflows. The WLE bit must be
set to enable loading of the WDT SFR, once loaded the
WLE bit is reset by hardware, this is to prevent erroneous
software from loading the WDT SFR.
The value loaded into the WDT defines the Watchdog
Interval (WI).
The range of intervals is from WDT = 00H which gives
524 ms to WDT = FFH which gives 2.048 ms.
14 PULSE WIDTH MODULATORS
The device has eight 6-bit Pulse Width Modulated (PWM)
outputs for analog control of e.g. volume, balance, bass,
treble, brightness, contrast, hue and saturation. The PWM
outputs generate pulse patterns with a repetition rate of
21.33 s, with the high time equal to the PWM SFR value
multiplied by 0.33 s. The analog value is determined by
the ratio of the high time to the repetition time, a D.C.
voltage proportional to the PWM setting is obtained by
means of an external integration network (low-pass filter).
14.1
The relevant PWM is enabled by setting the PWM enable
bit PWxE in the PWMx Control Register (where x = 0 to 7).
The high time is defined by the value PWxV<5:0>.
t
WI
=
12 2048
=
Watchdog Timer operation
PWM control
256 WDT
–
--------
f
osc
1
=
t
12 2048
=
256 WDT
–
Preliminary specification
--------------------- -
12 10
1
SAA55xx
2.048 ms
6
=
2.048 ms