saa5547ps NXP Semiconductors, saa5547ps Datasheet - Page 35

• Manufacturer Part Number: saa5547ps
• Description: Saa550x; Saa554x Tv Microcontrollers With Closed Captioning Cc And On-screen Display Osd
• Manufacturer: NXP Semiconductors

Philips Semiconductors
14.2
The device has a single 14-bit PWM that can be used for
Voltage Synthesis Tuning. The method of operation is
similar to the normal PWM except that the repetition period
is 42.66 s.
14.3
Two SFRs are used to control the TPWM, they are TDACL
and TDACH. The TPWM is enabled by setting the
TPWE bit in the TDACH SFR. The most significant bits
TD<13:7> alter the high period between 0 and 42.33 s.
The seven least significant bits TD<6:0> extend certain
pulses by a further 0.33 s, e.g. if TD<6:0> = 01H then
1 in 128 periods will be extended by 0.33 s, if
TD<6:0> = 02H then 2 in 128 periods will be extended.
The TPWM will not start to output a new value until TDACH
has been written to. Therefore, if the value is to be
changed, TDACL should be written before TDACH.
14.4
Four successive approximation Analog-to-Digital
Converters can be implemented in software by making use
of the on-board 8-bit Digital-to-Analog Converter and
Analog Comparator.
14.4.1
The control of the required analog input is done using the
channel select bits CH<1:0> in the SAD SFR, this selects
the required analog input to be passed to one of the inputs
of the comparator. The second comparator input is
generated by the DAC whose value is set by the bits
SAD<7:0> in the SAD and SADB SFRs. A comparison
between the two inputs is made when the start compare bit
ST in the SAD SFR is set, this must be at least one
instruction cycle after the SAD<7:0> value has been set.
The result of the comparison is given on VHI one
instruction cycle after the setting of ST.
14.4.2
The external analog voltage that is used for comparison
with the internally generated DAC voltage does not have
the same voltage range. The DAC has a lower reference
level of V
2000 Feb 23
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
Tuning Pulse Width Modulator (TPWM)
TPWM control
Software ADC (SAD)
SAD
SAD
SSA
and an upper reference level of V
CONTROL
INPUT VOLTAGE
DDP
.
35
The resolution of the DAC voltage with a nominal value is
3.3
value equivalent to V
V
Metal Oxide Semiconductor transistor. The reason for this
is that the input pins for the analog signals (P3.0 to P3.3)
are 5 V tolerant for normal port operations, i.e. when not
used as analog input. To protect the analog multiplexer
and comparator circuitry from the 5 V, a series transistor is
used to limit the voltage. This limiting introduces a voltage
drop equivalent to V
maximum value of V
calculations, the maximum input to the SAD should be
calculated as V
voltage in the range V
the same comparison value.
14.4.3
The SAD module incorporates a DC Comparator mode
which is selected using the DC_COMP control bit in the
SADB SFR. This mode enables the microcontroller to
detect a threshold crossing at the input to the selected
analog input pin (P3.0/ADC0, P3.1/ADC1, P3.2/ADC2 or
P3.3/ADC3) of the software ADC. A level sensitive
interrupt is generated when the analog input voltage level
at the pin falls below the analog output level of the SAD
DAC.
This mode is intended to provide the device with a
wake-up mechanism from Power-down or Idle mode when
a key-press on the front panel of the TV is detected.
The following software sequence should be used when
utilizing this mode for Power-down or Idle:
1. Disable INT1 using the IE SFR.
2. Set INT1 to level sensitive using the TCON SFR.
3. Set the DAC digital input level to the desired threshold
4. Enter DC Compare mode by setting the DC_COMP
5. Enable INT1 using the IE SFR.
6. Enter Power-down/Idle mode. Upon wake-up the SAD
DDP
256
level using SAD/SADB SFRs and select the required
input pin (P3.0/ADC0, P3.1/ADC1, P3.2/ADC2 or
P3.3/ADC3) using CH<1:0> in the SAD SFR.
enable bit in the SADB SFR.
should be restored to its conventional operating mode
by disabling the DC_COMP control bit.
V
13 mV. The external analog voltage has a lower
SAD DC
tn
, where V
DD(min)
COMPARATOR MODE
tn
tn
tn
SSA
is the threshold voltage for an N type
DDP
( 0.6 V) on the input voltage. The
is 0.75 V, therefore for worst case
0.75 V. Therefore, for an input
and an upper value equivalent to
to V
DDP
Preliminary specification
V
tn
the SAD returns
SAA55xx