m12l16161a Elite Semiconductor Memory Technology Inc., m12l16161a Datasheet - Page 13

• Manufacturer Part Number: m12l16161a
• Description: 512k X 16bit X 2banks Synchronous Dram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
Read & Write Cycle at Same Bank @Burst Length = 4
QC
*Note: 1.Minimum row cycle times is required to complete internal DRAM operation.
Elite Semiconductor Memory Technology Inc.
A10/AP
CLOCK
ADDR
CL=3
CL=2
DQ M
CKE
CAS
RAS
WE
BA
CS
2.Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
3.Access time from Row active command. tcc*(t
4.Ouput will be Hi-Z after the end of burst.(1,2,4,8 bit burst)
precharge. Last valid output will be Hi-Z(t
Burst can’t end in Full Page Mode.
0
Row Active
(A- Bank)
Ra
Ra
1
t
2
RCD
*Note3
t
R AC
3
*Note3
t
R AC
(A- Bank)
Ca0
Read
4
5
Qa0
t
S AC
6
t
RC
SHZ
Qa0
Qa1
t
t
O H
S AC
*Note1
*Note2
) after the clock.
7
Precharge
(A- Bank)
RCD
Qa1
Qa2
t
O H
+CAS latency-1)+t
8
Qa2
Qa3
9
HIGH
Qa3
t
S H Z
10
Row Active
(A- Bank)
*Note4
Rb
Rb
t
S H Z
11
SAC
*Note4
12
13
(A-Bank)
W r ite
Cb0
Db0
Db0
Revision : 2.7
Publication Date : Sep. 2008
14
Db1
Db1
M12L16161A
15
Db2
Db2
16
Db3
Db3
17
t
RDL
t
RDL
18
Precharge
13/29
(A- Bank)
: Don't care
19