PSMN2R0-30YL_10 NXP [NXP Semiconductors], PSMN2R0-30YL_10 Datasheet

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PSMN2R0-30YL_10

Manufacturer Part Number
PSMN2R0-30YL_10
Description
N-channel TrenchMOS logic level FET
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1. Product profile
1.1 General description
1.2 Features and benefits
1.3 Applications
1.4 Quick reference data
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
industrial and communications applications.
Table 1.
[1]
Symbol Parameter
V
I
P
Dynamic characteristics
Q
Q
Static characteristics
R
D
DS
tot
GD
G(tot)
DSon
High efficiency due to low switching
and conduction losses
Class-D amplifiers
DC-to-DC converters
Continuous current is limited by package.
PSMN2R0-30YL
N-channel TrenchMOS logic level FET
Rev. 03 — 7 January 2010
drain-source voltage T
drain current
total power
dissipation
gate-drain charge
total gate charge
drain-source
on-state resistance
Quick reference
Conditions
T
see
T
V
V
and
V
V
V
T
j
mb
mb
j
GS
DS
GS
DS
GS
≥ 25 °C; T
= 25 °C
Figure 1
= 25 °C; V
= 25 °C; see
15
= 12 V; see
= 12 V; see
= 4.5 V; I
= 4.5 V; I
= 10 V; I
j
D
and
≤ 175 °C
D
D
GS
= 15 A;
= 10 A;
= 10 A;
Figure 14
Figure 14
3
Figure 2
= 10 V;
Suitable for logic level gate drive
sources
Motor control
Server power supplies
[1]
Min
-
-
-
-
-
-
Product data sheet
Typ
-
-
-
7.5
30
1.55
Max
30
100
97
-
-
2
Unit
V
A
W
nC
nC
mΩ

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PSMN2R0-30YL_10 Summary of contents

Page 1

... PSMN2R0-30YL N-channel TrenchMOS logic level FET Rev. 03 — 7 January 2010 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET plastic package using TrenchMOS technology. This product is designed and qualified for use in industrial and communications applications. 1.2 Features and benefits ...

Page 2

... ° 100 j(init Ω; unclamped R GS All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 January 2010 PSMN2R0-30YL N-channel TrenchMOS logic level FET Graphic symbol mbb076 Version SOT669 Min Max - ...

Page 3

... Fig 2. Normalized total power dissipation as a function of mounting base temperature = All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 January 2010 PSMN2R0-30YL N-channel TrenchMOS logic level FET 03aa16 50 100 150 200 T (°C) mb 003aac529 10 μs 100 μs ...

Page 4

... Transient thermal impedance from junction to mounting base as a function of pulse duration PSMN2R0-30YL_3 Product data sheet Conditions see Figure All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 January 2010 PSMN2R0-30YL N-channel TrenchMOS logic level FET Min Typ Max - 0.4 1.28 003aac481 δ = ...

Page 5

... MHz see Figure 16 = 0.5 Ω 4 4.7 Ω R G(ext) All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 January 2010 PSMN2R0-30YL N-channel TrenchMOS logic level FET Min Typ Max Figure 11 1.3 1.7 2.15 0. ...

Page 6

... GS Fig 6. 003aac475 160 g fs (S) 140 120 100 100 150 I (A) D Fig 8. All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 January 2010 PSMN2R0-30YL N-channel TrenchMOS logic level FET Min Typ Max Figure 17 - 0.78 1 003aac474 ( 2.8 2.6 0 ...

Page 7

... V (V) 3 -60 GS Fig 12. Gate-source threshold voltage as a function of junction temperature All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 January 2010 PSMN2R0-30YL N-channel TrenchMOS logic level FET 003aac476 (V) GS 003a a c337 max typ min 0 ...

Page 8

... Q (nC) G Fig 16. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 January 2010 PSMN2R0-30YL N-channel TrenchMOS logic level FET GS(pl) V GS(th GS1 ...

Page 9

... Fig 17. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values PSMN2R0-30YL_3 Product data sheet 100 150 ° 0.0 0.2 0.4 0.6 0.8 All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 January 2010 PSMN2R0-30YL N-channel TrenchMOS logic level FET 003aac469 25 °C 1.0 V (V) SD © NXP B.V. 2010. All rights reserved ...

Page 10

... D E max 4.41 2.2 0.9 0.25 0.30 4.10 5.0 4.20 3.62 2.0 0.7 0.19 0.24 3.80 4.8 REFERENCES JEDEC JEITA MO-235 All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 January 2010 PSMN2R0-30YL N-channel TrenchMOS logic level FET detail ( 3.3 6.2 0.85 1.3 1.3 1.27 0.25 3.1 5.8 ...

Page 11

... Data sheet status Change notice Product data sheet - Product data sheet - Preliminary data sheet - All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 January 2010 PSMN2R0-30YL N-channel TrenchMOS logic level FET Supersedes PSMN2R0-30YL_2 PSMN2R0-30YL_1 - © NXP B.V. 2010. All rights reserved ...

Page 12

... All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 January 2010 PSMN2R0-30YL N-channel TrenchMOS logic level FET © NXP B.V. 2010. All rights reserved ...

Page 13

... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS — trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 January 2010 PSMN2R0-30YL N-channel TrenchMOS logic level FET © NXP B.V. 2010. All rights reserved ...

Page 14

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: PSMN2R0-30YL_3 All rights reserved. Date of release: 7 January 2010 ...

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