k9f3208w0a-tcb0 Samsung Semiconductor, Inc., k9f3208w0a-tcb0 Datasheet
k9f3208w0a-tcb0
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k9f3208w0a-tcb0 Summary of contents
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... Added CE don’t care mode during the data-loading and reading 0.2 1. Revised real-time map-out algorithm(refer to technical notes) 2. Removed erase suspend/resume mode 0.3 1. Changed device name - KM29W32000AT -> K9F3208W0A-TCB0 - KM29W32000AIT -> K9F3208W0A-TIB0 0.4 1. Changed invalid block(s) marking method prior to shipping - The invalid block(s) information is written the 1st or 2nd page of the invalid block(s) with 00h data ---> ...
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... K9F3208W0A-TCB0, K9F3208W0A-TIB0 Bit NAND Flash Memory FEATURES Voltage Supply : 2.7V ~ 5.5V Organization - Memory Cell Array : (4M + 128K)bit x 8bit - Data Register : (512 + 16)bit x8bit Automatic Program and Erase - Page Program : (512 + 16)Byte - Block Erase : (8K + 256)Byte - Status Register 528-Byte Page Read Operation - Random Access : 10 s(Max.) - Serial Page Access : 50ns(Min ...
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... K9F3208W0A-TCB0, K9F3208W0A-TIB0 Figure 1. FUNCTIONAL BLOCK DIAGRAM X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command Register CE Control Logic RE & High Voltage WE Generator CLE ALE WP Figure 2. ARRAY ORGANIZATION 32M : 8K Pages 1st half Page Register 2nd half Page Register ...
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... K9F3208W0A-TCB0, K9F3208W0A-TIB0 PRODUCT INTRODUCTION The K9F3208W0A is a 33Mbit(34,603,008 bit) memory organized as 8192 rows(pages) by 528 columns. Spare sixteen columns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data trans- fer between the I/O buffers and memory during page read and page program operations. The memory array is made cells that are serially connected to form a NAND structure ...
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... K9F3208W0A-TCB0, K9F3208W0A-TIB0 PIN DESCRIPTION Command Latch Enable(CLE) The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. Address Latch Enable(ALE) The ALE input controls the activating path for address to the internal address registers ...
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... Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING (Voltage reference to GND, K9F3208W0A-TCB0:T Parameter Symbol ...
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... K9F3208W0A-TCB0, K9F3208W0A-TIB0 VALID BLOCK Parameter Symbol Valid Block Number N NOTE : K9F3208W0A 1. The may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits erase or program factory-market bad blocks ...
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... K9F3208W0A-TCB0, K9F3208W0A-TIB0 AC Timing Characteristics for Command / Address / Data Input Parameter CLE Set-up Time CLE Hold Time CE Setup Time CE Hold Time WE Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time WE High Hold Time AC Characteristics for Operation ...
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... K9F3208W0A-TCB0, K9F3208W0A-TIB0 NAND Flash Technical Notes Invalid Block(s) Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor- mation regarding the invalid block( called as the invalid block information. Devices with invalid block(s) have the same quality level or as devices with all valid blocks and have the same AC and DC characteristics ...
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... K9F3208W0A-TCB0, K9F3208W0A-TIB0 NAND Flash Technical Notes (Continued) Error in write or read operation Over its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail- ure after erase or program, block replacement should be done ...
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... K9F3208W0A-TCB0, K9F3208W0A-TIB0 NAND Flash Technical Notes (Continued) Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Yes * No Erase Error I Yes Erase Completed : If erase operation results in an error, map out * the failing block and replace it with another block. ...
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... K9F3208W0A-TCB0, K9F3208W0A-TIB0 Pointer Operation of K9F3208W0A The K9F3208W0A has three modes to set the destination of the pointer. The pointer is set to "A" area by the "00h" command, to "B" area by the "01h" command, and to "C" area by the "50h" command. Table 1 shows the destination of the pointer, and figure 2 shows the block diagram of its operations ...
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... K9F3208W0A-TCB0, K9F3208W0A-TIB0 System Interface Using CE don’t-care. For a easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read- ing would provide significant savings in power consumption ...
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... K9F3208W0A-TCB0, K9F3208W0A-TIB0 * Command Latch Cycle CLE t CLS ALS ALE I Address Latch Cycle t CLE ALE I CLH ALH Command CLS ALS ...
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... K9F3208W0A-TCB0, K9F3208W0A-TIB0 * Input Data Latch Cycle CLE ALS WC ALE I/O ~ DIN Sequential Out Cycle after Read CE t REA RE I R/B NOTES : Transition is measured 200mV from steady state voltage with load DIN 1 ...
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... K9F3208W0A-TCB0, K9F3208W0A-TIB0 * Status Read Cycle CLE t CLS I READ1 OPERATION (READ ONE PAGE) CLE ALE I/O ~ 00h or 01h Column Page(Row) Address Address R/B t CLR t CLH CSTO t WHR 70h t WB ...
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... K9F3208W0A-TCB0, K9F3208W0A-TIB0 READ1 OPERATION (INTERCEPTED BY CE) CLE CE WE ALE RE I/O ~ 00h or 01h Column Address R/B READ2 OPERATION (READ ONE PAGE) CLE CE WE ALE RE 50h I R/B M Address AR2 Dout Dout N Page(Row) Address ...
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... K9F3208W0A-TCB0, K9F3208W0A-TIB0 SEQUENTIAL ROW READ OPERATION CLE CE WE ALE RE 00h I R/B M PAGE PROGRAM OPERATION CLE ALE RE I/O ~ 80h Sequential Data Column Page(Row) Input Command Address Address R/B Dout Dout Dout Dout ~ A 21 ...
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... K9F3208W0A-TCB0, K9F3208W0A-TIB0 BLOCK ERASE OPERATION (ERASE ONE BLOCK) CLE ALE RE I/O ~ 60h Block Address R/B Auto Block Erase Setup Command MANUFACTURE & DEVICE ID READ OPERATION CLE CE WE ALE RE I/O ~ 90h 00h 0 7 Read ID Command BERS ~ A DOH ...
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... K9F3208W0A-TCB0, K9F3208W0A-TIB0 DEVICE OPERATION PAGE READ Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command reg- ister along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera- tion ...
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... K9F3208W0A-TCB0, K9F3208W0A-TIB0 Figure 4. Read2 Operation CLE CE WE ALE R/B RE Start Add.(3Cycle) 50h I & Don't Care) Figure 5. Sequential Row Read1 Operation R/B I 00h Start Add.(3Cycle) 01h & (SE=L, 00h Command) 1st half array ...
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... K9F3208W0A-TCB0, K9F3208W0A-TIB0 Figure 6. Sequential Read2 Operation (SE=fixed low) R/B I 50h Start Add.(3Cycle & Don't Care) PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive bytes up to 528 single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed ten ...
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... K9F3208W0A-TCB0, K9F3208W0A-TIB0 BLOCK ERASE The Erase operation can erase on a block(8K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command(60h). Only address The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution ensures that memory contents are not accidentally erased due to external noise conditions ...
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... K9F3208W0A-TCB0, K9F3208W0A-TIB0 READ ID The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Two read cycles sequentially output the manufacture code(ECh), and the device code (E3h) respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 9 shows the operation sequence. ...
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... K9F3208W0A-TCB0, K9F3208W0A-TIB0 READY/BUSY The device has a R/ output that provides a hardware method of indicating the completion of a page program, erase and random B read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg- ister or random read is begin after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied ...
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Package Dimensions DATA PROTECTION The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be ...
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Package Dimensions PACKAGE DIMENSIONS 44(40) LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(II) 44(40) - TSOP2 - 400F #44(40) #1 18.81 Max. 0.741 18.41 0.10 0.725 0.004 0.805 0.35 0.10 0.032 0.014 0.004 FLASH MEMORY 0.25 0.010 #23(21) #22(20) 0.15 0.006 ...