k9f3208w0a-tcb0 Samsung Semiconductor, Inc., k9f3208w0a-tcb0 Datasheet - Page 23

• Manufacturer Part Number: k9f3208w0a-tcb0
• Description: 4m X 8 Bit Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

K9F3208W0A-TCB0, K9F3208W0A-TIB0
BLOCK ERASE
Figure 8. Block Erase Operation
The device contains a Status Register which may be read to find out whether program or erase operation is complete, and whether
the program or erase operation completed successfully. After writing 70h command to the command register, a read cycle outputs
the contents of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00h or 50h) should be given before sequential page read cycle.
The Erase operation can erase on a block(8K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase
Setup command(60h). Only address A
The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence
of setup followed by execution ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O
R/B
I/O
READ STATUS
Table2. Read Status Register Definition
0
~
7
I/O #
60h
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
Block Add. : A
Address Input(2Cycle)
13
9
~ A
to A
21
21
is valid while A
Reserved for Future
Device Operation
Program / Erase
Write Protect
D0h
Status
Use
0
) may be checked. Figure 8 details the sequence.
9
23
to A
t
BERS
12
is ignored. The addresses of the block to be erased to FFh.
"0" : Successful Program / Erase
"1" : Error in Program / Erase
"0"
"0"
"0"
"0"
"0"
"0" : Busy
"0" : Protected
70h
FLASH MEMORY
Definition
"1" : Not Protected
"1" : Ready
I/O
Fail
0
Pass