k9f3208w0a-tcb0 Samsung Semiconductor, Inc., k9f3208w0a-tcb0 Datasheet - Page 22

• Manufacturer Part Number: k9f3208w0a-tcb0
• Description: 4m X 8 Bit Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

K9F3208W0A-TCB0, K9F3208W0A-TIB0
R/B
I/O
PAGE PROGRAM
R/B
I/O
The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive
bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same
page without an intervening erase operation must not exceed ten. The addressing may be done in any random order in a block. A
page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded into the page register, fol-
lowed by a nonvolatile programming period where the loaded data is programmed into the appropriate cell. Serial data loading can
be started from 2nd half array. About the pointer operation, please refer to the attached technical notes.The serial data loading period
begins by inputting the Serial Data Input command(80H), followed by the three cycle address input and then serial data loading. The
bytes other than those to be programmed do not need to be loaded.
The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without perviously entering the
serial data will not initiate the programming process. The internal write controller automatically executes the algorithms and timings
necessary for program and verify, thereby freeing the CPU for other tasks. Once the program process starts, the Read Status Regis-
ter command may be entered, with RE and CE low, to read the status register. The CPU can detect the completion of a program
cycle by monitoring the R/B output, or the Status bit(I/O
mand are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O
checked(Figure 7). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command
register remains in Read Status command mode until another valid command is written to the command register.
Figure 6. Sequential Read2 Operation (SE=fixed low)
Figure 7. Program & Read Status Operation
0
0
~
~
7
7
80h
50h
(A
Don't Care)
Start Add.(3Cycle)
4
A
Address & Data Input
~ A
0
528 Byte Data
~ A
7
A
:
0
7
~ A
& A
3
9
& A
~ A
9
21
~ A
21
t
R
1st half array
10h
Data Field
Data Output
6
) of the Status Register. Only the Read Status command and Reset com-
1st
2nd half array
22
Spare Field
t
PROG
t
R
1st
2nd
Nth
Data Output
(16 Byte)
2nd
70h
FLASH MEMORY
t
R
I/O
Fail
0
Data Output
(16 Byte)
Nth
0
) may be
Pass