FSQ0565R_08 FAIRCHILD [Fairchild Semiconductor], FSQ0565R_08 Datasheet - Page 15

• Manufacturer Part Number: FSQ0565R_08
• Manufacturer: FAIRCHILD [Fairchild Semiconductor]

FSQ0565R, FSQ0765R Rev. 1.0.1
© 2008 Fairchild Semiconductor Corporation
uses a sync signal instead of directly monitoring the
output voltage. If the sync signal exceeds 8V, an OVP is
triggered, shutting down the SMPS. To avoid undesired
triggering of OVP during normal operation, there are 2
points to be considered which is depicted in Figure 32.
One is the making the peak voltage of the sync signal
should be designed below 6V and the other is that be
sure to make the spike of sync pin as los as possible not
to get longer than t
inductance shown at V
4.5 Thermal Shutdown with Hysteresis (TSD): The
SenseFET and the control IC are built in one package.
This makes it easy for the control IC to detect the
abnormally high temperature of the SenseFET. If the
temperature exceeds approximately 140°C, the thermal
shutdown triggers IC shutdown. The IC recovers its
operation when the junction temperature decreases
60°C from TSD temperature and V
voltage (V
5. Soft-Start: The FPS has an internal soft-start circuit
that increases PWM comparator inverting input voltage
with the SenseFET current slowly after it starts up. The
typical soft-start time is 17.5ms. The pulse width to the
power switching device is progressively increased to
establish the correct working conditions for transformers,
inductors, and capacitors. The voltage on the output
capacitors is progressively increased with the intention of
smoothly establishing the required output voltage. This
mode helps prevent transformer saturation and reduces
stress on the secondary diode during start-up.
V
V
Vcc_coil
sync
&V
CC
start
Improper OVP triggering
).
V
t
OVP
Figure 32. OVP Triggering
CC
Absolue max V
OVP
CC
V
V
V
OVP
SH2
V
Vcc_coil
CLAMP
(4.8V)
(8V)
winding coil.
by decreasing the leakage
CC
(20V)
CC
reaches start-up
FSQ0765R Rev.00
V
DC
t
OVP
N
N
pri
Vcc
15
6. Burst Operation: To minimize power dissipation in
standby mode, the FPS enters burst-mode operation. As
the load decreases, the feedback voltage decreases. As
shown in Figure 33, the device automatically enters
burst-mode when the feedback voltage drops below
V
output voltages start to drop at a rate dependent on
standby current load. This causes the feedback voltage
to rise. Once it passes V
resumes. The feedback voltage then falls and the
process repeats. Burst-mode operation alternately
enables and disables switching of the power SenseFET,
thereby reducing switching loss in standby mode.
7. Switching Frequency Limit: To minimize switching
loss and Electromagnetic Interference (EMI), the
MOSFET turns on when the drain voltage reaches its
minimum value in quasi-resonant operation. However,
this causes switching frequency to increases at light load
conditions. As the load decreases or input voltage
increases, the peak drain current diminishes and the
switching frequency increases. This results in severe
switching losses at light-load condition, as well as
intermittent switching and audible noise. These problems
create limitations for the quasi-resonant converter
topology in a wide range of applications.
To overcome these problems, FSQ-series employs a
frequency-limit function, as shown in Figures 34 and 35.
Once the SenseFET is turned on, the next turn-on is
prohibited during the blanking time (t
blanking time, the controller finds the valley within the
detection time window (t
shown in Figures 34 and Figure 35 (Cases A, B, and C).
BURL
FSQ0765R Rev.00
0.55V
0.35V
V
V
V
I
V
FB
DS
DS
O
set
O
Figure 33. Waveforms of Burst Operation
(350mV). At this point, switching stops and the
t1
Switching
disabled
W
) and turns on the MOSFET, as
t2 t3
BURH
Switching
disabled
(550mV), switching
B
www.fairchildsemi.com
). After the
t4
time