X1286 Intersil Corporation, X1286 Datasheet - Page 10

• Manufacturer Part Number: X1286
• Description: Intersil Real Time Clock/Calendar/CPU Supervisor with EEPROM X1286
• Manufacturer: Intersil Corporation

*n = 0 for Alarm 0: N = 1 for Alarm 1
Table 1. Clock/Control Memory Map
(except the status register), however, the WEL and
RWEL bits must be set using a two step process (See
section “Writing to the Clock/Control Registers.”)
The CCR is divided into 5 sections. These are:
1. Alarm 0 (8 bytes; non-volatile)
2. Alarm 1 (8 bytes; non-volatile)
3. Control (4 bytes; non-volatile)
4. Real Time Clock (8 bytes; volatile)
5. Status (1 byte; volatile)
Each register is read and written through buffers. The
non-volatile portion (or the counter portion of the RTC) is
updated only if RWEL is set and only after a valid write
operation and stop bit. A sequential read or page write
operation provides access to the contents of only one
section of the CCR per operation. Access to another sec-
tion requires a new operation. Continued reads or writes,
once reaching the end of a section, will wrap around to
the start of the section. A read or write can begin at any
address in the CCR.
It is not necessary to set the RWEL bit prior to writing
the status register. Section 5 supports a single byte
read or write only. Continued reads or writes from this
section terminates the operation.
REV 1.1 7/8/04
Addr.
003F
0037
0036
0035
0034
0033
0032
0031
0030
0013
0012
0011
0010
(EEPROM)
(SRAM)
Control
Status
Type
RTC
Name
SSEC
DTR
ATR
Reg
DW
MO
MN
INT
SR
YR
DT
HR
SC
BL
SS23
BAT
BP2
Y23
MIL
IM
0
0
0
0
0
0
0
7
SS22
AL1E
M22
BP1
AL1
Y22
S22
6
0
0
0
0
0
0
ATR5
SS21
AL0E
M21
BP0
AL0
Y21
D21
H21
S21
5
0
0
0
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ATR4
SS20
WD1
M20
FO1
Y20
G20
D20
H20
S20
4
0
0
0
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Additional
registers are read by performing a sequential read.
The read instruction latches all Clock registers into a
buffer, so an update of the clock does not change the
time being read. A sequential read of the CCR will not
result in the output of data from the memory array. At
the end of a read, the master supplies a stop condition
to end the operation and free the bus. After a read of
the CCR, the address remains at the previous address
+1 so the user can execute a current address read of
the CCR and continue reading the next Register.
ALARM REGISTERS
There are two alarm registers whose contents mimic the
contents of the RTC register, but add enable bits and
exclude the 24 hour time selection bit. The enable bits
specify which registers to use in the comparison between
the Alarm and Real Time Registers. For example:
– Setting the Enable Month bit (EMOn*) bit in combi-
nation with other enable bits and a specific alarm
time, the user can establish an alarm that triggers at
the same time once a year.
Bit
ATR3
SS13
WD0
M13
FO0
Y13
G13
D13
H13
S13
3
0
0
0
Read Only Read Only Read Only
Read Only Read Only Read Only
RWEL
DTR2
ATR2
SS12
M12
DY2
G12
D12
H12
Y12
S12
2
DTR1
ATR1
SS11
WEL
DY1
G11
D11
H11
M11
Y11
S11
1
(optional)
RTCF
DTR0
SS10
ATR0
DY0
G10
M10
Y10
D10
H10
S10
0
Range
0-99
0-99
1-12
1-31
0-23
0-59
0-59
0-6
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