X1286 Intersil Corporation, X1286 Datasheet - Page 16

• Manufacturer Part Number: X1286
• Description: Intersil Real Time Clock/Calendar/CPU Supervisor with EEPROM X1286
• Manufacturer: Intersil Corporation

Figure 7. Slave Address, Word Address, and Data Bytes (128 Byte pages)
REV 1.1 7/8/04
Bit 3 through Bit 1 of the slave byte specify the device
select bits. These are set to ‘111’.
The last bit of the Slave Address Byte defines the oper-
ation to be performed. When this R/W bit is a one, then
a read operation is selected. A zero selects a write
operation. Refer to Figure 7.
After loading the entire Slave Address Byte from the
SDA bus, the X1286 compares the device identifier
and device select bits with ‘1010111’ or ‘1101111’.
Upon a correct compare, the device outputs an
acknowledge on the SDA line.
Following the Slave Byte is a two byte word address.
The word address is either supplied by the master
device or obtained from an internal counter. On power
up the internal address counter is set to address 0h, so
a current address read of the EEPROM array starts at
address 0. When required, as part of a random read,
the master must supply the 2 Word Address Bytes as
shown in Figure 7.
In a random read operation, the slave byte in the
“dummy write” portion must match the slave byte in the
“read” section. That is if the random read is from the
array the slave byte must be 1010111x in both
instances. Similarly, for a random read of the Clock/
Control Registers, the slave byte must be 1101111x in
both places.
Array
CCR
A7
1
1
D7
0
Device Identifier
A14
0
1
A6
D6
A13
A5
D5
1
0
A12
D4
A4
0
1
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A11
D3
A3
1
1
A10
D2
A2
Write Operations
Byte Write
For a write operation, the device requires the Slave
Address Byte and the Word Address Bytes. This gives
the master access to any one of the words in the array
or CCR. (Note: Prior to writing to the CCR, the master
must write a 02h, then 06h to the status register in two
preceding operations to enable the write operation.
See “Writing to the Clock/Control Registers.” Upon
receipt of each address byte, the X1286 responds with
an acknowledge. After receiving both address bytes
the X1286 awaits the eight bits of data. After receiving
the 8 data bits, the X1286 again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition. The X1286 then begins
an internal write cycle of the data to the nonvolatile
memory. During the internal write cycle, the device
inputs are disabled, so the device will not respond to
any requests from the master. The SDA output is at high
impedance. See Figure 8.
A write to a protected block of memory is ignored, but
will still receive an acknowledge. At the end of the write
command, the X1286 will not initiate an internal write
cycle, and will continue to ACK commands.
Page Write
The X1286 has a page write operation. It is initiated in
the same manner as the byte write operation; but
instead of terminating the write cycle after the first data
byte is transferred, the master can transmit up to 127
1
D1
A9
A1
R/W
A8
A0
D0
Slave Address Byte
Byte 0
Word Address 1
Byte 1
Word Address 0
Byte 2
Data Byte
Byte 3
X1286
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