X1286 Intersil Corporation, X1286 Datasheet - Page 11

• Manufacturer Part Number: X1286
• Description: Intersil Real Time Clock/Calendar/CPU Supervisor with EEPROM X1286
• Manufacturer: Intersil Corporation

Table 1. Clock/Control Memory Map (Continued)
When there is a match, an alarm flag is set. The occur-
rence of an alarm can be determined by polling the
AL0 and AL1 bits or by enabling the IRQ output, using
it as hardware flag.
The alarm enable bits are located in the MSB of the
particular register. When all enable bits are set to ‘0’,
there are no alarms.
– The user can set the X1286 to alarm every Wednes-
– A daily alarm for 9:30PM results when the EHRn*
*n = 0 for Alarm 0: N = 1 for Alarm 1
REAL TIME CLOCK REGISTERS
Clock/Calendar Registers (SSEC, SC, MN, HR, DT,
MO, YR)
These registers depict BCD representations of the
time. As such, SSEC (1/100 Second) range from 00 to
99, SC (Seconds) and MN (Minutes) range from 00 to
59, HR (Hour) is 1 to 12 with an AM or PM indicator
(H21 bit) or 0 to 23 (with MIL=1), DT (Date) is 1 to 31,
MO (Month) is 1 to 12, YR (Year) is 0 to 99. The SSEC
register is read-only.
REV 1.1 7/8/04
Addr.
000D
000C
000F
000E
000B
000A
0009
0008
0007
0006
0005
0004
0003
0002
0001
0000
day at 8:00 AM by setting the EDWn*, the EHRn*
and EMNn* enable bits to ‘1’ and setting the DWAn*,
HRAn* and MNAn* Alarm registers to 8:00 AM
Wednesday.
and EMNn* enable bits are set to ‘1’ and the HRAn*
and MNAn* registers are set to 9:30 PM.
(EEPROM)
(EEPROM)
Alarm1
Alarm0
Type
DWA1
DWA0
MOA1
MNA1
MOA0
MNA0
Name
YRA1
HRA1
SCA1
YRA0
HRA0
SCA0
DTA1
DTA0
Y2K1
Y2K0
Reg
EDW1
EDW0
EMO1
EMN1
EMO0
EMN0
EHR1
ESC1
EHR0
ESC0
EDT1
EDT0
7
Unused - Default = RTC Year value (No EEPROM) – Future expansion
Unused - Default = RTC Year value (No EEPROM) - Future expansion
A1M22
A0M22
A1S22
A0S22
6
0
0
0
0
0
0
0
0
A1M21
A0M21
A1D21
A1H21
A0D21
A0H21
A1S21
A0S21
5
0
0
0
0
www.intersil.com
Read-only - Default = 20h
Read-only - Default = 20h
A1G20
A1D20
A1H20
A1M20
A0G20
A0D20
A0H20
A0M20
A1S20
A0S20
4
0
0
Date of the Week Register (DW)
This register provides a Day of the Week status and
uses three bits DY2 to DY0 to represent the seven days
of the week. The counter advances in the cycle 0-1-2-
3-4-5-6-0-1-2-… The assignment of a numerical value
to a specific day of the week is arbitrary and may be
decided by the system software designer. The default
value is defined as ‘0’.
24 Hour Time
If the MIL bit of the HR register is 1, the RTC uses a
24-hour format. If the MIL bit is 0, the RTC uses a 12-
hour format and H21 bit functions as an AM/PM indica-
tor with a ‘1’ representing PM. The clock defaults to
standard time with H21=0.
Leap Years
Leap years add the day February 29 and are defined
as those years that are divisible by 4. Years divisible by
100 are not leap years, unless they are also divisible
by 400. This means that the year 2000 is a leap year,
the year 2100 is not. The X1286 does not correct for
the leap year in the year 2100.
STATUS REGISTER (SR)
The Status Register is located in the CCR memory
map at address 003Fh. This is a volatile register only
and is used to control the WEL and RWEL write enable
Bit
A1G13
A1D13
A1H13
A1M13
A0G13
A0D13
A0H13
A0M13
A1S13
A0S13
3
0
0
A1G12
A1M12
A0G12
A0M12
A1D12
A1H12
A1S12
A0D12
A0H12
A0S12
DY2
DY2
2
A1G11
A1M11
A0G11
A0M11
A1D11
A1H11
A1S11
A0D11
A0H11
A0S11
DY1
DY1
1
(optional)
A1G10
A1M10
A0G10
A0M10
A1D10
A1H10
A1S10
A0D10
A0H10
A0S10
DY0
DY0
0
Range
1-12
1-31
0-23
0-59
0-59
1-12
1-31
0-23
0-59
0-59
0-6
0-6
20
20
X1286
11 of 26
20h
00h
00h
00h
00h
00h
00h
20h
00h
00h
00h
00h
00h
00h