X1286 Intersil Corporation, X1286 Datasheet - Page 15

• Manufacturer Part Number: X1286
• Description: Intersil Real Time Clock/Calendar/CPU Supervisor with EEPROM X1286
• Manufacturer: Intersil Corporation

Figure 4. Valid Data Changes on the SDA Bus
Figure 5. Valid Start and Stop Conditions
Figure 6. Acknowledge Response From Receiver
The device will respond with an acknowledge after rec-
ognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave
Address Byte. If a write operation is selected, the
device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for:
– The Slave Address Byte when the Device Identifier
– All Data Bytes of a write when the WEL in the Write
– The 2nd Data Byte of a Status Register Write Opera-
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
REV 1.1 7/8/04
and/or Select bits are incorrect
Protect Register is LOW
tion (only 1 data byte is allowed)
SCL from
Master
Data Output
from Transmitter
Data Output
from Receiver
SDA
SCL
SDA
SCL
Start
Data Stable
Start
1
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Data Change
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
DEVICE ADDRESSING
Following a start condition, the master must output a
Slave Address Byte. The first four bits of the Slave
Address Byte specify access to either the EEPROM
array or to the CCR. Slave bits ‘1010’ access the
EEPROM array. Slave bits ‘1101’ access the CCR.
When shipped from the factory, EEPROM array is
UNDEFINED, and should be programmed by the cus-
tomer to a known state.
Data Stable
8
Stop
Acknowledge
9
X1286
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