LM9801CCV NSC [National Semiconductor], LM9801CCV Datasheet - Page 23

• Manufacturer Part Number: LM9801CCV
• Description: Greyscale/24-Bit Color Linear CCD Sensor Processor
• Manufacturer: NSC [National Semiconductor]

Figure 4 shows the output stage of a typical CCD and the
Applications Information
4 4 Correlated Double Sampler (CDS)
resulting output waveform
Capacitor C1 converts the electrons coming from the CCD’s
shift register to an analog voltage The source follower out-
put stage (Q2) buffers this voltage before it leaves the CCD
Q1 resets the voltage across capacitor C1 in between every
pixel at intervals 2 and 5 When Q1 is on the output signal
(OS) is at its maximum After Q1 turns off (period 3) the OS
level
(V
thermal noise from the ON resistance of Q1 and other
sources of error When the shift register clock ( 1) makes a
low to high transition (period 4) the electrons from the next
pixel flow into C1 The charge across C1 now contains the
voltage proportional to the number of electrons plus
V
period 3 and that voltage is subtracted from the OS at the
end of period 4 the V
noise on the signal is reduced ( V
b
Double Sampling
The LM9801 implements CDS with two switched-capacitor
S H amplifiers The S Hs acquire a signal within a 50 ns
window which can be placed anywhere in the pixel period
with 25 ns precision See Diagrams 7 and 8 for more de-
tailed timing information
4 5 CIS Mode
The LM9801 provides some support for CIS (Contact Image
Sensor) devices by offering a sampling mode for capturing
positive going signals as opposed to the CCD’s negative
going signal
RESIDUAL
RESIDUAL
V
RESIDUAL
represents
) V
an error term If OS is sampled at the end of
e
RESIDUAL
V
SIGNAL
the
FIGURE 4 CDS
RESIDUAL
) This is the principal of Correlated
includes charge injection from Q1
residual
term is canceled and the
voltage
SIGNAL
(Continued)
a
across
TL H 12814 – 31
V
RESIDUAL
C1
23
While CIS devices do not usually have a reference level with
which to perform correlated double sampling many have a
very repeatable reset level which can be used as a black
reference allowing the LM9801 to perform pseudo CDS on
the signal When the Signal Polarity bit is set to a zero the
LM9801 expects a positive going signal typically from a CIS
device When the Signal Polarity bit is set to a one the
LM9801 expects a negative going signal typically from a
CCD sensor
4 6 Offset DAC
The 4 bit plus sign Offset DAC is used to compensate for
DC offsets due to the correlated double sampling stage
The offset can be corrected in 31 steps of 0 42 ADC LSB
size between
comes betore the PGA so any offset errors at this stage are
multiplied by the gain of the PGA The calibration procedure
described in Section 5 0 demonstrates how to use the DAC
to eliminate offset errors before scanning begins
Note that this DAC is programmed during LM9801 calibra-
tion configuration and is not meant to compensate for pixel-
to-pixel CCD offset errors CDS cancels the pixel-rate offset
errors
4 7 Programmable Gain Amplifier (PGA)
The PGA provides 8 bits of pixel-to-pixel gain correction
over a 0 dB to 9 dB (x1 to x3) range After the input signal is
sampled and held by the CDS stage it is amplified by the
gain indicated by the data (‘‘PGA Code’’) on the CD0– CD7
databus using the formula
4 8 Offset Add Bit
In addition to the Offset DAC there is a bit in the configura-
tion register which when set adds a positive 2 LSB offset at
the output of the PGA This offset ensures that any offset
between the output of the PGA and the ADC is positive so
that no dark level information is lost due to negative offsets
The calibration procedure described in Section 5 0 demon-
strates how to set this bit
FIGURE 5 CIS vs CCD Output Signals
Gain
b
6 3 and
V
V
e
a
1
6 3 LSBs Note that the DAC
a
PGA code
256
1 95
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