LM9801CCV NSC [National Semiconductor], LM9801CCV Datasheet - Page 8

• Manufacturer Part Number: LM9801CCV
• Description: Greyscale/24-Bit Color Linear CCD Sensor Processor
• Manufacturer: NSC [National Semiconductor]

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Pin Descriptions
RS
TR
OS
REF IN
REF OUT
REF OUT
V
V
MCLK
SYNC
SDI
SDO
SCLK
CS
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TEST1
TEST2
1
2
HI
MID
Configuration Register I O
Digital Output CCD clock signal phase 1
Digital Output CCD clock signal phase 2
Digital Output Reset pulse for the CCD
Digital Output Transfer pulse for the CCD
Analog Input This is the OS (Output
Signal) from the CCD The maximum peak
signal that can be accurately digitized is
equal to the voltage at REF IN typically
1 225V
Analog Inputs These two pins are the
system reference voltage inputs and
should be tied together to a 1 225V voltage
source and bypassed to AGND with a 0 1
Analog Output This reference voltage is
developed internally by the LM9801 and is
equal to 3 times REF IN It should be
bypassed to AGND with a 0 1 F
monolithic capacitor
Analog Output This reference voltage is
developed internally by the LM9801 and is
equal to 2 times REF IN It should be
bypassed to AGND using a 0 1 F
monolithic capacitor
Analog Inputs Outputs These pins are
used for testing the device during
manufacture and should be left
unconnected
Digital Input This is the 20 MHz (typical)
master system clock
Digital Input A low-to-high transition on this
input begins a line scan operation The line
scan operation terminates when this input
is taken low
Digital Input Serial Data Input pin
Digital Output Serial Data Output pin
Digital Input This is the serial data clock
used to clock data in through SDI and out
through SDO SCLK is asynchronous to
MCLK Input data is latched and output
data is changed on the rising edge of
SCLK
Digital Input This is the Chip Select signal
for writing to the Configuration Register
through the serial interface This input must
be low in order to communicate with the
Configuration Register This pin is used for
serial I O only–it has no effect on any
other section of the chip
F monolithic capacitor
CCD Driver Signals
General Digital I O
Analog I O
8
CD0 (LSB)– Digital Inputs Correction Coefficient
CD7 (MSB)
CCLK
DD0 (LSB)– Digital Outputs Pixel Output Databus This
DD7 (MSB)
EOC
RD
V
AGND
V
DGND
V
DGND
NC
A
D
D(I O)
(I O)
Databus This is the 8-bit data path for the
gain adjust PGA used during line scan
Digital Output This is the signal that is used
to clock the Gain coefficients into the
LM9801 Data is latched on the rising edge
of CCLK
data bus outputs the 8-bit digital output data
during line scan
Digital Output This is the End of Conversion
signal from the ADC indicating that new
pixel data is available
Digital Input Taking this input low places
the data stored in the output latch on the
bus When this input is high the DD0– DD7
bus is in TRI-STATE
This is the positive supply pin for the analog
supply It should be connected to a voltage
source of
a 0 1 F monolithic capacitor in parallel with
a 10 F tantalum capacitor
This is the ground return for the analog
supply
This is the positive supply pin for the digital
supply It should be connected to a voltage
source of
a 0 1 F monolithic capacitor
This is the ground return for the digital
supply
This is the positive supply pin for the digital
supply for the LM9801’s I O It should be
connected to a voltage source of
a
0 1 F monolithic capacitor If the supply for
this pin is different than the supply for V
and V
10 F tantalum capacitor
This is the ground return for the digital
supply for the LM9801’s I O
All pins marked NC (no connect) should be
left floating Do not tie NC pins to ground
power supplies or any other potential or
signal
5V and bypassed to DGND
Digital Coefficient I O
Digital Output I O
D
Analog Power
Digital Power
it should also be bypassed with a
a
a
5V and bypassed to AGND with
5V and bypassed to DGND with
NC
(I O)
a
with a
3V to
A