LM9801CCV NSC [National Semiconductor], LM9801CCV Datasheet - Page 31

• Manufacturer Part Number: LM9801CCV
• Description: Greyscale/24-Bit Color Linear CCD Sensor Processor
• Manufacturer: NSC [National Semiconductor]

Applications Information
Suggested timing for CIS devices is
As CIS sensors approach pixel rates of 1 MHz and above
(corresponding to MCLK frequencies of 8 MHz and above)
the voltage during the reset level becomes less stable mak-
ing it difficult to perform CDS on the output (Figure 22) The
solution is to create the ground reference externally short-
ing the LM9801’s input to ground for half of the time using
the 1 clock as shown in Figure 23
Mode
RS Pulse Width
RS Pulse Polarity
used)
RS Pulse Position
Sample Reference Position
Sample Signal Position
TR Pulse Width
TR- 1 Guardband
TR Polarity
Signal Polarity
Dummy Pixels
Optical Black Pixels
( Value given in CCD datasheet)
1
2 RS TR Enable
e
FIGURE 22 High Speed CIS Waveforms
FIGURE 23 High Speed CIS Interface
0 (Standard Mode)
e
1
e
e
e
e
0
2
e
e
e
0
0 (2 MCLKs)
e
0
0
0 (or 1 if circuit of Figure 21 is
e
10
e
0 0 1 1
14
e
2
(Continued)
TL H 12814 – 49
TL H 12814 – 50
31
Figure 24 produces a 1
10 0 HINTS AND COMMON SYSTEM DESIGN
PROBLEMS
10 1 Reading and Writing to the Configuration Register
The Configuration Register sends and receives data LSB
(Least Significant Byte) first Some microcontrollers send
out data MSB (Most Significant Byte) first The order of the
bits must be reversed to when using these microcontrollers
Note Unlike the LM9800 the SYNC pin does not have to be held high to
10 2 Setting the Dummy and Optical Black Pixel
Registers
The minimum value in the Dummy Pixels register is 2 (a
value of 0 or 1 will cause errors in the EOC and CCLK tim-
ing) Note that the value in this register should be equal to 1
plus the actual number of dummy pixels in the CCD For
example if the CCD being used with the LM9801 has 12
dummy pixels this register should be set to 13 The mini-
mum number in the Optical Black Pixels register is 1
10 3 Stretching the TR- 1 Guardband
Some CCDs (Sony’s ILX514 ILX518 and ILX524 for exam-
ple) require a TR to
(2 MCLKs) provided by the LM9801 The circuit shown in
guardband between the end of the
next edge of
pulse width register to 2
generate a 1 s pulse inside that TR period to send to the
CCD
send or receive data to or from the Configuration Register
FIGURE 24 Stretching the TR- 1 Guardband
1 This is done by setting the LM9801’s TR
1 guardband greater than the 100 ns
s
s and using the 74HC4538 to
ROG (transfer) pulse with a
ROG pulse and the
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