LM9801CCV NSC [National Semiconductor], LM9801CCV Datasheet - Page 29

• Manufacturer Part Number: LM9801CCV
• Description: Greyscale/24-Bit Color Linear CCD Sensor Processor
• Manufacturer: NSC [National Semiconductor]

Figure 15 shows the interface between the LM9801 and a
Applications Information
8 0 A TYPICAL GREYSCALE APPLICATION
typical greyscale even odd output CCD the TCD1250 The
interface for most other CCDs will be similar the only differ-
ence being the values for the series resistors (if required)
The clamp capacitor value is determined as shown in Sec-
tion 4 2 The resistor values are usually given in the CCD’s
datasheet If the datasheet’s requirement is given as a par-
ticular rise fall time the resistor can be chosen using the
graph of 1
Resistance vs Load Capacitance graph in the Typical
Performance Characteristics section Given the required
rise time and the input capacitance of the input being driven
the resistor value can be estimated from the graph
These are the Configuration Register parameters recom-
mended for use as a starting point for most even odd
CCDs
Mode
RS Pulse Width
RS Pulse Polarity
RS Pulse Position
Sample Reference Position
Sample Signal Position
TR Pulse Width
TR- 1 Guardband
TR Polarity
Signal Polarity
Dummy Pixels
Optical Black Pixels
( Value given in CCD datasheet)
1
FIGURE 15 Greyscale CCD Interface Example
2 RS TR Enable
e
1 (Even Odd mode)
e
2 RS and TR Rise Times Through a Series
0
e
e
e
e
1
2
e
e
e
0
0 (1 MCLK)
e
0
10
0
e
5
e
1 1 1 1
8
e
14
(Continued)
TL H 12814 – 42
29
ence portion appears during the last 2 MCLKs (following the
The Mode is set to Even Odd RS Pulse Width is set to its
minimum value and RS polarity is positive The timing
shown in Figure 16 is determined by the RS SR and SS
registers The RS pulse position (RS) is set to 10 dividing
the pixel period so that the signal portion is available for the
first 5 MCLKs following a 1 clock edge and the black refer-
1 MCLK wide reset pulse) Sample Reference (SR) is set to
14 so it samples the black reference just before the next 1
clock edge Sample Signal (SS) is set to 8 so it samples the
black reference just before the next reset pulse These val-
ues can be adjusted to account for differences in CCDs
CCD data delays settling time etc but this is often not
necessary
All 4 digital outputs ( 1
TR pulse width is set to the minimum 20 MCLKs as is the
guardband between 1 and TR Either of these settings can
be increased if necessary
The TR polarity is positive as is the RS polarity Some
CCDs may require one or both of these signals to be invert-
ed in which case the corresponding bit can be set to a ‘‘1’’
If there is an inverting buffer between the LM9801 and the
CCD these bits may be used to correct the output polarity
at the CCD Note that if
should be used as
as
Since this is a CCD sensor the Signal Polarity is set to a 1
(inverted) to match the CCD’s output signal The number of
dummy pixels and optical black reference pixels are given in
the CCD’s datasheet The dummy pixel register should be
programmed with the number of dummy pixels in the CCD
register should contain 17) The optical black reference reg-
ister should be programmed with the number of optical
black pixels in the CCD
a
1 (for example if the CCD has 16 dummy pixels then the
2 at the CCD ( Figure 17 )
FIGURE 17
FIGURE 16 Typical Even Odd Timing
1 at the CCD and
1 and 2 After Inversion
2 RS and TR) are enabled The
1 and
2 are inverted then
1 should be used
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