LM9801CCV NSC [National Semiconductor], LM9801CCV Datasheet - Page 30

• Manufacturer Part Number: LM9801CCV
• Description: Greyscale/24-Bit Color Linear CCD Sensor Processor
• Manufacturer: NSC [National Semiconductor]

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Figure 19 shows the analog and digital circuitry required to
Applications Information
The PGA gain coefficient register and PGA Gain Source bit
are used during calibration (see Section 5 0) The Power
Down bit should be set to 0 for normal operation The Offset
Add bit is also programmed during calibration
The VGA and Offset DAC bits are programmed during cali-
bration (Section 5 0) The Test Mode bits should always be
set to ‘‘0’’
9 0 TYPICAL CIS APPLICATION
Many CIS sensors (such as those made by Dyna Image
Corporation) have only one clock input a transfer signal
and an output signal that is referred to ground (Figure 18)
connect a typical Dyna CIS to the LM9801
Because the CIS requires only one clock with a duty cycle of
less than 50% the LM9801’s RS output is used as the
CIS’s CLK source
D flip-flop is used to lengthen the transfer pulse (SI or ‘‘Shift
In’’ on the CIS) so that it overlaps the first RS pulse and
meets the timing requirement of the CIS (see Figure 20 )
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FIGURE 19 Minimum CIS Interface
FIGURE 18 CIS Waveforms
1 and
2 are not used The 74HC74
(Continued)
TL H 12814– 45
TL H 12814– 46
30
21) This forces the output voltage to zero for the time that
The final ‘‘trick’’ required to interface a CIS to the LM9801 is
the generation of optical black pixels for the LM9801 to
clamp to at the beginning of a line Unlike CCDs CIS devic-
es do not have a sequence of optical black pixels at the
beginning of a line the first pixel out of a CIS is valid image
data There are several ways to create black pixels for the
LM9801 to clamp to
The simplest solution is to physically place a light shield
(black plastic tape or metal) over the first 10 or so pixels
This reduces the voltage output of the CIS to nearly 0V
which is adequate for the LM9801 to clamp to This has the
side effect of slightly reducing the number of active pixels
available for image capture
A second option is to artifically generate ‘‘black’’ pixels by
holding the CLOCK input high for 10 or so RS pulses (Figure
the CLOCK input is high and only one active image pixel is
lost The BLACK signal could be generated by the ASIC ex-
ternal logic that generates a pulse on the first rising edge of
RS after the TR pulse
FIGURE 21 Generating Artificial Black Pixels
FIGURE 20 CIS Interface Digital Timing
TL H 12814 – 47
TL H 12814 – 48