ISL6322_07 INTERSIL [Intersil Corporation], ISL6322_07 Datasheet - Page 21

• Manufacturer Part Number: ISL6322_07
• Description: Four-Phase Buck PWM Controller with Integrated MOSFET Drivers and I2C Interface for Intel VR10, VR11, and AMD Applications
• Manufacturer: INTERSIL [Intersil Corporation]

V
R
Output-Voltage Offset Programming
The ISL6322 allows the designer to accurately adjust the
offset voltage by connecting a resistor, R
pin to VCC or GND. When R
and VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (I
If R
regulated to 0.4V, and I
offset current flowing through the resistor between VDIFF
and FB will generate the desired offset voltage which is
equal to the product (I
shown in Figures 7 and 8.
Once the desired output offset voltage has been determined,
use the following formulas to set R
For Negative Offset (connect R
For Positive Offset (connect R
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of normal operation. They direct the ISL6322
to do this by making changes to the VID inputs. The ISL6322
is required to monitor the DAC inputs and respond to
on-the-fly VID changes in a controlled manner, supervising a
safe output voltage transition without discontinuity or
disruption. The DAC mode the ISL6322 is operating in
determines how the controller responds to a dynamic VID
change.
R
R
OFS
OFS
+
-
OFS
OFS
VDIFF
VCC
FIGURE 7. POSITIVE OFFSET OUTPUT VOLTAGE
OFS
R
=
=
FB
OFS
is connected to ground, the voltage across it is
--------------------------
V
--------------------------
V
FB
0.4 R
1.6 R
OFFSET
OFFSET
⋅
⋅
PROGRAMMING
ISL6322
FB
FB
CURRENT
I
MIRROR
OFS
1:1
OFS
OFS
x R
OFS
flows out of the FB pin. The
21
OFS
FB
OFS
OFS
I
OFS
). These functions are
is connected between OFS
OFS
to VCC):
) to flow into the FB pin.
to GND):
E/A
:
REF
OFS
, from the OFS
VCC
+
-
(EQ. 12)
(EQ. 13)
1.6V
ISL6322
INTEL DYNAMIC VID TRANSITIONS
When in Intel VR10 or VR11 mode, the ISL6322 checks the
VID inputs on the positive edge of an internal 3MHz clock. If
a new code is established and it remains stable for 3
consecutive readings (1μs to 1.33μs), the ISL6322
recognizes the new code and changes the internal DAC
reference directly to the new level. The Intel processor
controls the VID transitions and is responsible for
incrementing or decrementing one VID step at a time. In
VR10 and VR11 settings, the ISL6322 will immediately
change the internal DAC reference to the new requested
value as soon as the request is validated, which means the
fastest recommended rate at which a bit change can occur is
once every 2μs. In cases where the reference step is too
large, the sudden change can trigger overcurrent or
overvoltage events.
In order to ensure the smooth transition of output voltage
during a VR10 or VR11 VID change, a VID step change
smoothing network is required. This network is composed of
an internal 1kΩ resistor between the DAC and the REF pin,
and the external capacitor C
ground. The selection of C
for 1-bit VID change and the allowable delay time.
Assuming the microprocessor controls the VID change at
1 bit every T
given by Equation 14.
As an example, for a VID step change rate of 5μs per bit, the
value of C
C
V
R
REF
OFS
OFS
+
FIGURE 8. NEGATIVE OFFSET OUTPUT VOLTAGE
-
VDIFF
=
GND
R
0.001 S
FB
OFS
REF
FB
VID
PROGRAMMING
( ) T
is 5600pF based on Equation 14.
, the relationship between C
ISL6322
⋅
VID
I
CURRENT
OFS
MIRROR
VCC
1:1
REF
REF
is based on the time duration
, between the REF pin and
I
OFS
E/A
REF
REF
February 15, 2007
and T
GND
(EQ. 14)
FN6328.1
+
VID
-
0.4V
is