ISL6322_07 INTERSIL [Intersil Corporation], ISL6322_07 Datasheet - Page 27

• Manufacturer Part Number: ISL6322_07
• Description: Four-Phase Buck PWM Controller with Integrated MOSFET Drivers and I2C Interface for Intel VR10, VR11, and AMD Applications
• Manufacturer: INTERSIL [Intersil Corporation]

Individual Channel Overcurrent Limiting
The ISL6322 has the ability to limit the current in each
individual channel without shutting down the entire regulator.
This is accomplished by continuously comparing the sensed
currents of each channel with a constant 170μA OCL
reference current as shown in Figure 14. If a channel’s
individual sensed current exceeds this OCL limit, the UGATE
signal of that channel is immediately forced low, and the
LGATE signal is forced high. This turns off the upper
MOSFET(s), turns on the lower MOSFET(s), and stops the
rise of current in that channel, forcing the current in the
channel to decrease. That channel’s UGATE signal will not
be able to return high until the sensed channel current falls
back below the 170μA reference.
I
The ISL6322 includes an I
user programmability of four of the controller’s operating
parameters. The operating parameters that can be adjusted
through the I
To adjust these four parameters, data transmission from the
main microprocessor to the ISL6322 and vice versa must take
place through the two wire I
the I
and the SCL line, which is a clock signal used to synchronize
sending/receiving of the data.
2
1. Voltage Margining Offset: The output voltage can be
2. Adaptive Deadtime Control: Selects between LGATE
3. Overvoltage Trip Level: Selects the overvoltage
4. Switching Frequency: The switching frequency can be
FIGURE 15. OVERCURRENT BEHAVIOR IN HICCUP MODE
C Bus Interface
0A
0V
positively offset up to +787.5mV in 12.5mV increments.
Detect and PHASE Detect deadtime control schemes as
described in the User Selectable Adaptive Deadtime
Control Techniques section.
protection trip threshold as described in the Overvoltage
Protection section.
increased by a fixed +15% or +30%, or can be decreased
by -15% or -30%.
2
C bus consist of the SDA line, over which all data is sent,
OUTPUT CURRENT, 50A/DIV
2
OUTPUT VOLTAGE,
500mV/DIV
C are:
2
2
C bus interface which allows for
C bus interface. The two wires of
3ms/DIV
27
ISL6322
Both SDA and SCL are bidirectional lines, externally connected
to a positive supply voltage via a pull-up resistor. Pull-up
resistor values should be chosen to limit the input current to
less then 3mA. When the bus is free, both lines are HIGH. The
output stages of ISL6322 have an open drain/open collector in
order to perform the wired-AND function. Data on the I
can be transferred up to 100Kbps in the standard-mode or up to
400Kbps in the fast-mode. The level of logic “0” and logic “1” is
dependent on associated value of V
specification table. One clock pulse is generated for each data
bit transferred. The ISL6322 is a “SLAVE only” device, so the
SCL line must always be controlled by an external master.
It is important to note that the I
only works once the voltage on the VCC pin has risen above
the POR rising threshold. The I
active until the voltage on the VCC pin falls back below the
falling POR threshold level.
Data Validity
The data on the SDA line must be stable during the HIGH
period of the SCL, unless generating a START or STOP
condition. The HIGH or LOW state of the data line can only
change when the clock signal on the SCL line is LOW. Refer
to Figure 16.
START and STOP Conditions
As shown in Figure 17, a START (S) condition is a HIGH to
LOW transition of the SDA line while SCL is HIGH.
The STOP (P) condition is a LOW to HIGH transition on the
SDA line while SCL is HIGH. A STOP condition must be sent
before each START condition.
Byte Format
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant
bit first (MSB) and the least significant bit last (LSB).
SDA
SCL
SDA
SCL
CONDITION
START
S
FIGURE 17. START AND STOP WAVEFORMS
DATA VALID
DATA LINE
STABLE
FIGURE 16. DATA VALIDITY
ALLOWED
CHANGE
OF DATA
2
2
C interface of the ISL6322
C will continue to remain
DD
as per electrical
February 15, 2007
CONDITION
STOP
2
P
C bus
FN6328.1