FIN224AC_08 FAIRCHILD [Fairchild Semiconductor], FIN224AC_08 Datasheet

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FIN224AC_08

Manufacturer Part Number
FIN224AC_08
Description
22-Bit Bi-Directional Serializer/Deserializer
Manufacturer
FAIRCHILD [Fairchild Semiconductor]
Datasheet
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.5
Features
Applications
Ordering Information
µSerDes
22-Bit Bi-Directional Serializer/Deserializer
FIN224ACGFX
FIN224ACMLX
Industry smallest 22-bit Serializer/ Deserializer pair
Low power for minimum impact on battery life
– Multiple power-down modes
100nA in standby mode, 5mA typical operating
conditions
Highly rolled LVCMOS edge rate option to meet
regulatory requirements
Cable reduction: 25:4 or greater
Differential signaling:
––90dBm EMI when using CTL in lab conditions
–Minimized shielding
–Minimized EMI filter
–Minimum susceptibility to external interference
Up to 22 bits in either direction
Voltage translation from 1.65V to 3.6V
High ESD protection: > 15kV HBM
Parallel I/O power supply (V
Can support Microcontroller or RGB pixel interface
Image sensors
Small displays
– LCD, cell phone, digital camera, portable gaming,
printer, PDA, video camera, automotive
Number
Order
definition of “green” please visit http://www.fairchildsemi.com/company/green/rohs_green.html
All standard Fairchild Semiconductor products are RoHS compliant and many are also “GREEN” or going green. For Fairchild’s’
TM
is a trademark of Fairchild Semiconductor Corporation.
FIN224AC
Temperature
-30 to +70°C
-30 to +70°C
Operating
Range
DDP
) range, 1.65V - 3.6V
42-Ball Ultra Small Scale Ball Grid Array (USS-BGA),
JEDEC MO-195, 3.5mm Wide (Slow LVCMOS Edge Rate)
40-Terminal Molded Leadless Package (MLP), Quad,
JEDEC MO-220, 6mm Square (Slow LVCMOS Edge Rate)
Package Description
Description
The FIN224AC µSerDes™ is a low-power serializer/
deserializer (SerDes) that can help minimize the cost
and power of transferring wide signal paths. Through the
use of serialization, the number of signals transferred
from one point to another can be significantly reduced.
Typical reduction is 4:1 to 6:1 for unidirectional paths.
For bidirectional operation, using half duplex for multiple
sources, it is possible to reach signal reduction close to
10:1. Through the use of differential signaling, shielding
and EMI filters can also be minimized, further reducing
the cost of serialization. The differential signaling is also
important for providing a noise-insensitive signal that can
withstand radio and electrical noise sources. Major
reduction in power consumption allows minimal impact
on battery life in ultra-portable applications. It is possible
to use a single PLL for most applications including bi-
directional operation.
FIN224AC to FIN24AC Comparison
Up to 20% power reduction
Double wide CKP pulse on FIN224AC, Mode 3
Rolled edge rate for deserializer outputs on
FIN224AC, for single display applications
Same voltage range
Same pinout and package
Click here for this datasheet
translated into Korean!
Tape and Reel
Tape and Reel
www.fairchildsemi.com
Packing
Method
May 2008

Related parts for FIN224AC_08

FIN224AC_08 Summary of contents

Page 1

FIN224AC 22-Bit Bi-Directional Serializer/Deserializer Features Industry smallest 22-bit Serializer/ Deserializer pair ■ Low power for minimum impact on battery life ■ – Multiple power-down modes ■ 100nA in standby mode, 5mA typical operating conditions Highly rolled LVCMOS edge rate option ...

Page 2

Basic Concept LVCMOS 22 Functional Block Diagram CKREF STROBE DP[21:22] DP[1:20] DP[23:24] CKP S1 S2 DIRI © 2006 Fairchild Semiconductor Corporation FIN224AC Rev.1.1.5 CTL FIN224AC Serializer 4 Figure 1. Conceptual Diagram PLL 0 I cksint Serializer Control Serializer Deserializer Deserializer ...

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Terminal Description Terminal Number of I/O Type Name DP[1:20] I/O DP[21:22] I DP[23:24] O CKREF IN STROBE IN CKP OUT DSO+ / DSI- DIFF-I/O DSO- / DSI+ CKSI+ DIFF-IN CKSI- CKSO+ DIFF-OUT CKSO DIRI IN DIRO ...

Page 4

Connection Diagrams 42 MBGA Package 3.5mm x 4.5mm (.5mm Pitcth) (Top View © 2006 Fairchild Semiconductor Corporation FIN224AC Rev.1.1.5 DP[9] 1 DP[10] 2 DP[11] 3 DP[12] 4 ...

Page 5

Control Logic Circuitry The FIN224AC has the ability to be used as a 22-bit seri- alizer or a 22-bit deserializer. Pins S1 and S2 must be set to accommodate the clock reference input frequency range of the serializer. Table 1 ...

Page 6

Serializer Operation Mode The serializer configurations are described in the follow- ing sections. The basic serialization circuitry works essentially identically in these modes, but the actual data and clock streams differ depending on if CKREF is the same as the ...

Page 7

LVCMOS Data I/O The LVCMOS input buffers have a nominal threshold value equal to half V . The input buffers are only oper- DD ational when the device is operating as a serializer. When the device is operating as a ...

Page 8

Application Mode Diagrams SerDes Serializer U20 U20 TP6 TP6 VDDP A6 PIXCLK_M CKREF B5 STROBE F6 DIRI F5 GPIO_MODE DP24 J4 DP23 J3 DP22 F3 LCD_ENABLE_M DP21 J2 LCD_VSYNC_M DP20 J1 LCD_HSYNC_M DP19 F2 LCD17_M DP18 ...

Page 9

Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera- ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi- tion, ...

Page 10

DC Electrical Characteristics Values are for over-supply voltage and operating temperature ranges, unless otherwise specified. Typical values are given for V = 2.775V and values refer to the current flowing out of the pins. Voltages are referenced ...

Page 11

Power Supply Currents Typical values are given for V DD device and negative values refer to the current flowing out of the pins. Voltages are referenced to GROUND unless otherwise specified (except ΔV OD Symbol Parameter VDDA Serializer Static Supply ...

Page 12

AC Electrical Characteristics Characteristics at recommended over-supply voltage and operating temperature ranges, unless otherwise specified. Typical values are given for V DD device and negative values means current flowing out of the pins. Voltages are referenced to GROUND unless other- ...

Page 13

Notes : 3. Skew is measured from either the rising or falling edge of CKSO clock to the rising or falling edge of data (DSO). Signals are edge aligned. Both outputs should have identical load conditions for this test to ...

Page 14

AC Loading and Waveforms t ROLH 80% 80% 20% DPn Figure 7. LVCMOS Output Load and Transition Times t CLKT 90% 10% t TCP V IH CKREF 50 CPWH CPWL Figure 9. LVCMOS Clock Parameters © 2006 ...

Page 15

AC Loading and Waveforms t TPPLD1 CKS0 Figure 13. PLL Power-Down Time Note: If S1(2) transitioning then S2(1) must = 0 for test to be valid © 2006 Fairchild Semiconductor Corporation FIN224AC Rev.1.1.5 (Continued) t TPPLD0 CKREF ...

Page 16

Tape and Reel Specification MLP Embossed Tape Dimension Dimensions are in millimeters Package ±0.1 ±0.1 ±0. 5.35 5.35 1. 6.30 6.30 ...

Page 17

Physical Dimensions 0.15 C PIN #1 IDENT 0.80 MAX 0.10 C 0.08 C 0.05 0.00 SEATING PLANE 0.50 (DATUM B) 0.50 NOTES: A. CONFORMS TO JEDEC REGISTRATION MO-220, VARIATION WJJD-2 WITH EXCEPTION THAT THIS IS A SAWN VERSION.. B. DIMENSIONS ...

Page 18

Physical Dimensions (Continued) 2X 0.10 C TERMINAL A1 CORNER INDEX AREA (QA CONTROL VALUE) 1.00 MAX 0. SEATING PLANE Figure 17. 42-Ball, Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide Note: Click here ...

Page 19

Fairchild Semiconductor Corporation FIN224AC Rev.1.1.5 19 www.fairchildsemi.com ...

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