FIN3383 FAIRCHILD [Fairchild Semiconductor], FIN3383 Datasheet
FIN3383
Related parts for FIN3383
FIN3383 Summary of contents
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... FIN3385 • FIN3383 Low Voltage 28-Bit Flat Panel Display Link Serializers General Description The FIN3385 and FIN3383 transform 28 bit wide parallel LVTTL (Low Voltage TTL) data into 4 serial LVDS (Low Voltage Differential Signaling) data streams. A phase- locked transmit clock is transmitted in parallel with the data steam over a separate LVDS link ...
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Pin Descriptions Pin Names I/O Type Number of Pins TxIn I 28/21 TxCLKIn I TxOut O TxOut O TxCLKOut O TxCLKOut O R_FB I PwrDn I PLL PLL GND I LVDS LVDS GND I ...
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Absolute Maximum Ratings Power Supply Voltage ( TTL/CMOS Input/Output Voltage LVDS Input/Output Voltage LVDS Output Short Circuit Current (I ) OSD Storage Temperature Range (T ) STG Maximum Junction Temperature ( Lead Temperature ( ...
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AC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified. Symbol Parameter t Transmit Clock Period TCP t Transmit Clock (TxCLKIn) HIGH Time TCH t Transmit Clock Low Time TCL t TxCLKIn Transition Time (Rising and Failing) ...
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FIGURE 1. Differential LVDS Output DC Test Circuit AC Loading and Waveforms Note: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVTTL/CMOS I/O. Depending on the valid strobe edge of transmitter, the TxCLKIn ...
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AC Loading and Waveforms FIGURE 5. Transmitter Input Clock Transition Time FIGURE 6. Transmitter Clock In to Clock Out Delay (Rising Edge Strobe) FIGURE 7. Transmitter Power-Down Delay Note: The information in this diagram shows the relationship between clock out ...
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AC Loading and Waveforms FIGURE 9. Transmitter Output Pulse Bit Position Note: This jitter pattern is used to test the jitter response (Clock Out) of the device over the power supply range with worst jitter 3ns (cycle-to-cycle) clock input. The ...
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AC Loading and Waveforms Note: The 16-grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical strips across the display. FIGURE 11. “16 Grayscale” ...
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Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...