FIN24AGFX FAIRCHILD [Fairchild Semiconductor], FIN24AGFX Datasheet - Page 8

• Manufacturer Part Number: FIN24AGFX
• Description: Low Voltage 24-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges (Preliminary)
• Manufacturer: FAIRCHILD [Fairchild Semiconductor]

www.fairchildsemi.com
PLL Circuitry
The CKREF input signal is used to provide a reference to
the PLL. The PLL will generate internal timing signals
capable of transferring data at 26 times the incoming
CKREF signal. The output of the PLL is a Bit Clock that is
used to serialize the data. The bit clock is also sent source
synchronously with the serial data stream.
There are two ways to disable the PLL. The PLL can be
disabled by entering the Mode 0 state (S1
PLL will disable immediately upon detecting a LOW on
both the S1 and S2 signals. When any of the other modes
are entered by asserting either S1 or S2 HIGH and by pro-
Application Mode Diagrams
Unidirectional Data Transfer
Figure 8 shows the basic operation diagram when a pair of
SerDes is configured in an unidirectional operation mode.
Master Operation: The device will...
(Please refer to Figure 8)
1. During power-up the device will be configured as a
2. Accept CKREF_M word clock and generate a bit clock
3. Receive
4. Generate and transmit serialized data on the DS sig-
5. Generate an embedded word clock for each strobe sig-
serializer based on the value of the DIRI signal.
with embedded word boundary. This bit clock will be
sent to the slave device through the CKSO port.
STROBE_M.
nals which is source synchronous with CKSO.
nal.
parallel
FIGURE 8. Simplified Block Diagram for Unidirectional Serializer and Deserializer
data
on
the
rising
S2
edge
0). The
of
8
viding a CKREF signal the PLL will power-up and goes
through a lock sequence. One must wait the specified num-
ber of clock cycles prior to capturing valid data into the par-
allel port.
An alternate way of powering down the PLL is by stopping
the CKREF signal either HIGH or LOW. Internal circuitry
detects the lack of transitions and shuts the PLL and serial
I/O down. Internal references will not however be disabled
allowing for the PLL to power-up and re-lock in a lesser
number of clock cycles than when exiting Mode 0. When a
transition is seen on the CKREF signal the PLL will once
again be reactivated.
Slave Operation: The device will...
1. Be configured as a deserializer at power-up based on
2. Accept an embedded word boundary bit clock on CKSI.
3. Deserialize the DS Data stream using the CKSI input
4. Write parallel data onto the DP_S port and generate
the value of the DIRI signal.
clock.
the CKP_S. CKP_S will only be generated when a valid
data word occurs.
Preliminary