FIN3383MTD FAIRCHILD [Fairchild Semiconductor], FIN3383MTD Datasheet
FIN3383MTD
Related parts for FIN3383MTD
FIN3383MTD Summary of contents
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... TTL interfaces. Ordering Code: Order Number Package Number FIN3383MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide FIN3384MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide ...
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Block Diagrams Functional Diagram for FIN3385 and FIN3383 Receiver Functional Diagram for FIN3386 and FIN3384 www.fairchildsemi.com 2 ...
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TRANSMITTERS Pin Descriptions Pin Names I/O Type Number of Pins TxIn I 28/21 TxCLKIn TxOut O 4/3 TxOut O 4/3 TxCLKOut O TxCLKOut O R_FB I 1 PwrDn I PLL PLL ...
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RECEIVERS Pin Descriptions Number Pin Names I/O Type of Pins RxIn I 4/3 Negative LVDS Differential Data Input RxIn I 4/3 Positive LVDS Differential Data Input RxCLKIn I 1 Negative LVDS Differential Clock Input RxCLKIn I 1 ...
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Transmitter and Receiver Power-Up/Power-Down Operation Truth Table The outputs of the transmitter remain in the High-Impedance state until the power supply reaches 2V. The following table shows the operation of the transmitter during power-up and power-down and operation of the ...
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Absolute Maximum Ratings Power Supply Voltage ( TTL/CMOS Input/Output Voltage LVDS Input/Output Voltage LVDS Output Short Circuit Current (I ) OSD Storage Temperature Range (T ) STG Maximum Junction Temperature ( Lead Temperature ( ...
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Transmitter AC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified. Symbol Parameter t Transmit Clock Period TCP t Transmit Clock (TxCLKIn) HIGH Time TCH t Transmit Clock Low Time TCL t TxCLKIn Transition Time (Rising and ...
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Receiver DC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified. (Note 16) Symbol Parameter LVTTL/CMOS DC Characteristics V Input High Voltage IH V Input Low Voltage IL V Output High Voltage OH V Output Low Voltage ...
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Receiver AC Electrical Characteristics (66MHz) Symbol Parameter t Receiver Clock Output (RxCLKOut) Period RCOP t RxCLKOut LOW Time RCOL t RxCLKOut HIGH Time RCOH t RxOut Valid Prior to RxCLKOut RSRC t RxOut Valid After RxCLKOut RHRC t RxCLKOut LOW ...
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FIGURE 1. Differential LVDS Output DC Test Circuit Note A: For all input pulses Note B: C includes all probe and jig capacitance. L FIGURE 2. Differential Receiver Voltage Definitions and Propagation Delay and Transition Time Test Circuit ...
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AC Loading and Waveforms Note: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVTTL/CMOS I/O. Depending on the valid strobe edge of transmitter, the TxCLKIn can be either rising or falling edge data ...
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AC Loading and Waveforms FIGURE 7. Transmitter Outputs Channel-to-Channel Skew Note: For the receiver with falling-edge strobe, the definition of setup/hold time will be slightly different from the one with rising-edge strobe. The clock refer- ence point is the time ...
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AC Loading and Waveforms FIGURE 11. Receiver Phase Lock Loop Set Time FIGURE 12. Transmitter Power-Down Delay FIGURE 13. Receiver Power-Down Delay (Continued) 13 www.fairchildsemi.com ...
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AC Loading and Waveforms Note: The information in this diagram shows the relationship between clock out and the first data bit. A 2-bit cycle delay is guaranteed when the MSB is out- put from the transmitter. FIGURE 14. 28 Parallel ...
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AC Loading and Waveforms FIGURE 16. Transmitter Output Pulse Bit Position FIGURE 17. Receiver Input Bit Position (Continued) 15 www.fairchildsemi.com ...
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AC Loading and Waveforms Note the budget for the cable skew and source clock skew plus ISI (Inter-Symbol Interference). RSKM Note: The minimum and maximum pulse position values are based on the bit position of each of the ...
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AC Loading and Waveforms Note: The 16-grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical strips across the display. FIGURE 21. “16 Grayscale” ...
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Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...