FIN24C_06 FAIRCHILD [Fairchild Semiconductor], FIN24C_06 Datasheet
FIN24C_06
Related parts for FIN24C_06
FIN24C_06 Summary of contents
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FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer Features Low power for minimum impact on battery life ■ – Multiple power-down modes – AC coupling with DC balance 100nA in standby mode, 5mA typical operating ■ conditions Cable reduction: 25:4 or greater ■ ...
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Functional Block Diagram CKREF STROBE DP[m+1:24] DP[1:m] Note: I Control CKP S1 S2 DIRI ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 Word PLL 0 Boundary Generator I cksint Serializer Control Serializer oe Deserializer Deserializer cksint ...
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Terminal Description Terminal Name I/O Type DP[1:20] I/O DP[21:24 CKREF IN STROBE IN CKP OUT DSO+ / DSI– DIFF-I/O DSO– / DSI+ CKSI+, CKSI– DIFF-IN CKSO+, CKSO– DIFF-OUT DIRI IN DIRO OUT V ...
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Connection Diagrams Figure 2. Terminal Assignments for MLP (Top View (Top View) ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 DP[9] 1 DP[10] 2 DP[11] 3 DP[12] 4 ...
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Control Logic Circuitry The FIN24C has four signals that are selectable as two unidirectional inputs and two unidirectional outputs four unidirectional inputs or four unidirectional outputs. These are often used by applications for control signals. The mode signals ...
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Control Mode When operating in 4-bit control mode, the master device must be configured as MODE 2 ( and the slave device must be configured as MODE 1 ( 1). ...
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Serializer Operation Mode The serializer configuration is described in the following sections. The basic serialization circuitry works essentially the same in these modes, but the actual data and clock streams differ depending on if CKREF is the same as the ...
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Serializer Operation Mode Serializer Operation: (Figure 6), DIRI = 1, No CKREF CKSI DP[1:24] WORD n-1 STROBE DSO CKS0 No Data Figure 6. Serializer Timing Diagram Using Provided Bit Clock (No CKREF) ©2005 Fairchild ...
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Deserializer Operation Mode The operation of the deserializer is only dependent upon the data received on the DSI data signal pair and the CKSI clock signal pair. The following two sections describe the operation of the deserializer under two distinct ...
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Embedded Word Clock Operation The FIN24C sends and receives serial data source syn- chronously with a bit clock. The bit clock has been modi- fied to create a word boundary at the end of each data word. The word boundary ...
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From – Serializer From Control + To – Deserializer Figure 10. Bi-Directional Differential I/O Circuitry PLL Circuitry The CKREF input signal is used to provide a reference to the PLL. The PLL generates internal timing signals capa- ble of ...
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REFCK Sending Unit DATA [0:23] V Figure 12. 24-Bit Unidirectional Serializer and Deserializer REFCK Control CNTL[0:3] Unit DATA [0:19] PwrDwn Figure 13. Unidirectional Control, Bi-directional Data Interface Flex Circuit Design Guidelines The serial I/O information is transmitted at a high ...
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Absolute Maximum Ratings The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not ...
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DC Electrical Characteristics Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified. Symbol Parameter LVCMOS I/O V Input High Voltage IH V Input Low Voltage IL V Output High Voltage OH V Output Low Voltage OL ...
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Power Supply Currents Symbol Parameter I V Serializer Static Supply DDA1 DDA Current I V Deserializer Static Supply DDA2 DDA Current I V Serializer Static Supply DDS1 DDS Current V Deserializer Static Supply DDS Current I V Power-Down Supply Current ...
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AC Electrical Characteristics Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified. Symbol Parameter SERIALIZER INPUT OPERATING CONDITIONS t CKREF Clock Period TCP (10 MHz–20 MHz) f CKREF Frequency Relative to REF Strobe Frequency t CKREF ...
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Notes: 4. Typical Values are given for V device and negative values refer to current flowing out of pins. Voltage is referenced to GROUND unless otherwise specified (except ΔV and Skew is measured from either the rising ...
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AC Loading and Waveforms Input Figure 14. Differential CTL Output DC Test Circuit DP[1:12] 666h CKREF CKS0- CKS0 Note: The “worst-case” test pattern produces a maximum toggling of ...
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AC Loading and Waveforms Setup Time t STC STROBE DP[1:12] Hold Time STROBE DP[1:12] Data Setup: MODE0 = “0” or “1”, MODE1 = “1”, SER/DES = “1” Figure 19. Serial Setup and Hold Time Data Valid CKP Data DP[1:12] t ...
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AC Loading and Waveforms t S_DS CKSI- V DIFF=0 CKSI+ DSI DIFF=0 ID DSI- Figure 25. Differential Input Setup and Hold Times t TPPLD0 CKREF CKS0 Note: CKREF Signal can be stopped either HIGH or LOW. Figure ...
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Tape and Reel Specification Dimensions are in millimeters unless otherwise noted. BGA Embossed Tape Dimension ±0.1 ±0.1 ±0.05 Package 3.5 x 4.5 TBD TBD 1.55 Note: 10. ...
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Tape and Reel Specification Dimensions are in millimeters unless otherwise noted. MLP Embossed Tape Dimension ±0.1 ±0.1 ±0.05 Package 5.35 5.35 1. ...
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Physical Dimensions Dimensions are in millimeters unless otherwise noted. 2X 0.10 C TERMINAL A1 CORNER INDEX AREA (QA CONTROL VALUE) 1.00 MAX 0. SEATING PLANE Figure 31. Pb-Free, 42-Ball, Ultra Small Scale Ball Grid Array (USS-BGA), ...
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Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 32. Pb-Free, 40-Terminal, Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 (DATUM A) 24 www.fairchildsemi.com ...
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TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ACEx™ FACT Quiet Series™ ActiveArray™ GlobalOptoisolator™ Bottomless™ GTO™ Build it Now™ ...