ADUC847BCP8-5 AD [Analog Devices], ADUC847BCP8-5 Datasheet
ADUC847BCP8-5
Related parts for ADUC847BCP8-5
ADUC847BCP8-5 Summary of contents
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FEATURES High resolution Σ-∆ ADCs Two independent 24-bit ADCs on the ADuC845 Single 24-bit ADC on the ADuC847 and single 16-bit ADC on the ADuC848 ADC input channels on all parts 24-bit no missing codes 22-bit rms ...
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ADuC845/ADuC847/ADuC848 TABLE OF CONTENTS Specifications..................................................................................... 4 Abosolute Maximum Ratings ....................................................... 10 ESD Caution................................................................................ 10 Pin Configuration and Function Descriptions........................... 11 General Description ....................................................................... 15 8052 Instruction Set ................................................................... 18 Timer Operation......................................................................... 18 ALE............................................................................................... 18 External Memory Access ........................................................... 18 Complete ...
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Power-On Reset Operation........................................................88 Power Consumption ...................................................................88 Power-Saving Modes ..................................................................88 Grounding and Board Layout Recommendations .................89 Other Hardware Considerations...............................................90 REVISION HISTORY 6/04—Changed from Rev Rev. A Changes to Figure 5.........................................................................17 Changes to Figure 6.........................................................................18 Changes to Figure 7.........................................................................19 Changes ...
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ADuC845/ADuC847/ADuC848 1 SPECIFICATIONS DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz crystal; all specifications T ADC, unless otherwise noted. Core speed = 1.57 MHz (default ...
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Parameter 2 Normal Mode Rejection 50 Hz/ AIN 2 Analog Input Current Analog Input Current Drift Average Input Current Average Input Current Drift 2 Absolute AIN Voltage Limits Absolute AIN Voltage Limits 2 EXTERNAL REFERENCE INPUTS REFIN(+) to ...
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ADuC845/ADuC847/ADuC848 Parameter AUXILIARY ADC ANALOG INPUTS (ADuC845 Only Differential Input Voltage Ranges Bipolar Mode (ADC1CON Unipolar Mode (ADC1CON Average Analog Input Current Analog Input Current Drift Absolute AIN/AINCOM Voltage 2, 7 Limits 2 Normal ...
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Parameter TRANSDUCER BURNOUT CURRENT SOURCES AIN+ Current AIN− Current Initial Tolerance at 25°C Drift EXCITATION CURRENT SOURCES Output Current Initial Tolerance at 25°C Drift Initial Current Matching at 25°C Drift Matching Line Regulation ( Load Regulation 2 Output ...
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ADuC845/ADuC847/ADuC848 Parameter LOGIC OUTPUTS (All Digital Outputs except XTAL2 Output High Voltage Output Low Voltage OL 2 Floating State Leakage Current Floating State Output Capacitance START-UP TIME At Power-On After Ext RESET in Normal ...
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Parameter PWM −Fxtal −Fvco TIC 3 V Power Consumption 11, 12 Normal Mode DV Current DD AV Current DD 11, 12 Power-Down Mode DV Current DD AV Current DD 1 Temperature range is for ADuC845BS; for the ADuC847BS and ADuC848BS ...
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ADuC845/ADuC847/ADuC848 ABOSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 2. Parameter AV to AGND DGND DGND DGND DD 1 AGND to DGND ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS P1.0/AIN1 1 PIN 1 2 IDENTIFIER P1.1/AIN2 P1.2/AIN3/REFIN2 P1.3/AIN4/REFIN2– ADuC845/ADuC847/ADuC848 AGND 6 REFIN– 7 TOP VIEW REFIN+ ...
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ADuC845/ADuC847/ADuC848 Pin No: Pin No: 52-MQFP 56-CSP Mnemonic 7 7 REFIN− REFIN P1.4/AIN5 10 10 P1.5/AIN6 11 11 P1.6/AIN7/IEXC1 12 12 P1.7/AIN8/IEXC2 13 13 AINCOM/DAC 14 14 DAC ---- 15 AIN9 ---- 16 AIN10 15 17 ...
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Pin No: Pin No: 52-MQFP 56-CSP Mnemonic 25 27 P3.7/RD 20, 34, 48 22, 36 21, 35, 47 23, 37, DGND 38 SCLK ( SDATA P2.0–P2.7 28–31, 30–33, 36–39 39–42 ...
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ADuC845/ADuC847/ADuC848 Pin No: Pin No: 52-MQFP 56-CSP Mnemonic 43–46, 46–49, P0.0–P0.7 49–52 52– input output supply. 1 Type Description I/O These pins are part of Port 0, which is an 8-bit open-drain bidirectional ...
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GENERAL DESCRIPTION The ADuC845, ADuC847, and ADuC848 are single-cycle, 12.58 MIPs, 8052 core upgrades to the ADuC834 and ADuC836. They include additional analog inputs for applications requiring more ADC channels. The ADuC845, ADuC847, and ADuC848 are complete smart transducer front ...
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ADuC845/ADuC847/ADuC848 AIN1 56 AIN2 1 AIN3 2 AIN4 3 BUF AIN5 9 AIN AIN6 10 MUX AIN7 11 AUXILIARY ADC AIN8 12 Σ-∆ ADC AIN9* 15 AIN10* 16 AINCOM 13 BAND GAP ...
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AIN1 56 AIN2 1 AIN3 2 AIN4 BUF PGA 3 AIN5 9 AIN AIN6 10 MUX AIN7 11 AIN8 12 AIN9* 15 AIN10* 16 AINCOM 13 BAND GAP REFERENCE REFIN+ 8 ...
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ADuC845/ADuC847/ADuC848 AIN1 56 AIN2 1 AIN3 2 AIN4 3 BUF AIN5 9 AIN AIN6 10 MUX AIN7 11 AIN8 12 AIN9* 15 AIN10* 16 AINCOM 13 BAND GAP REFERENCE REFIN+ 8 DETECT ...
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COMPLETE SFR MAP ISPI WCOL SPE SPIM CPOL CPHA FFH 0 FEH 0 FDH 0 FCH 0 FBH 0 FAH F7H 0 F6H 0 F5H 0 F4H 0 F3H 0 F2H MDO MDE MCO MDI I2CM I2CRS EFH 0 EEH ...
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ADuC845/ADuC847/ADuC848 FUNCTIONAL DESCRIPTION 8051 INSTRUCTION SET Table 4. Optimized Single-Cycle 8051 Instruction Set Mnemonic Arithmetic A A,Rn ADD A,@Ri ADD A,dir ADD A,#data ADDC A,Rn ADDC A,@Ri ADDC A,dir ADD A,#data SUBB A,Rn SUBB A,@Ri SUBB A,dir SUBB A,#data INC ...
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Mnemonic RLC RRC A Data Transfer MOV A,Rn MOV A,@Ri MOV Rn,A MOV @Ri,A MOV A,dir MOV A,#data MOV Rn,#data MOV dir,A MOV Rn, dir MOV dir, Rn MOV @Ri,#data MOV dir,@Ri MOV @Ri,dir MOV dir,dir MOV ...
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ADuC845/ADuC847/ADuC848 Mnemonic SJMP rel JC rel JNC rel JZ rel JNZ rel DJNZ Rn,rel LJMP 3 LCALL addr16 JB bit,rel JNB bit,rel JBC bit,rel CJNE A,dir,rel CJNE A,#data,rel CJNE Rn,#data,rel CJNE @Ri,#data,rel DJNZ dir,rel Miscellaneous NOP 1 One cycle is ...
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BANKS SELECTED VIA 20H BITS IN PSW 1FH 11 18H 17H 10 10H 0FH 01 08H 07H 00 00H Figure 8. Lower 128 Bytes of Internal Data Memory Internal XRAM The ADuC845, ADuC847, and ADuC848 contain 2 ...
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ADuC845/ADuC847/ADuC848 SPECIAL FUNCTION REGISTERS (SFRs) The SFR space is mapped into the upper 128 bytes of internal data memory space and accessed by direct addressing only. It provides an interface between the CPU and all on-chip periph- erals. A block ...
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Power Control Register (PCON) The PCON SFR contains bits for power-saving options and general-purpose status flags as listed in Table 6. SFR Address: 87H Power-On Default: 00H Bit Addressable: No Table 6. PCON SFR Bit Designations Bit No. Name Description ...
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ADuC845/ADuC847/ADuC848 ADC CIRCUIT INFORMATION The ADuC845 incorporates two 10-channel (8-channel on the MQFP package) 24-bit Σ-∆ ADCs, while the ADuC847 and ADuC848 each incorporate a single 10-channel (8-channel on the MQFP package) 24-bit and 16-bit Σ-∆ ADC. Each part also ...
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Signal Chain Overview (Chop Enabled, CHOP = 0) With the CHOP bit = 0 (see the ADCMODE SFR bit designa- tions in Table 24), the chopping scheme is enabled. This is the default condition and gives optimum performance in terms ...
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ADuC845/ADuC847/ADuC848 This offset is removed by performing a running average of 2. This average by 2 means that the settling time to any change in programming of the ADC is twice the normal conversion time, while an asynchronous step change ...
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ADC Noise Performance with Chop Enabled (CHOP = 0) Table 10, Table 11, Table 12, and Table 13 show the output rms noise and output peak-to-peak resolution in bits (rounded to the nearest 0.5 LSB) for some typical output update ...
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ADuC845/ADuC847/ADuC848 Signal Chain Overview with Chop Disabled (CHOP = 1) With CHOP = 1, chop is disabled and the available output rates vary from 16. 1.365 kHz. The range of applicable SF words is from 3 to 255. ...
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ADC Noise Performance with Chop Disabled (CHOP = 1) Table 14, Table 15, Table 16, and Table 17 show the output rms noise and output peak-to-peak resolution in bits (rounded to the nearest 0.5 LSB) for some typical output update ...
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ADuC845/ADuC847/ADuC848 AUXILIARY ADC (ADUC845 ONLY) Table 18. ADuC845 Typical Output RMS Noise (µV) vs. Update Rate with Chop Enabled SF Word Data Update Rate (Hz) 13 105.03 23 59.36 27 50.56 69 19.79 255 5.35 Table 19. ADuC845 Typical Peak-to-Peak ...
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When the resulting voltage measured is full scale, the transducer has gone open circuit. When the voltage measured this indicates that the transducer has gone short circuit. The current sources work over the normal ...
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ADuC845/ADuC847/ADuC848 enabled for any SF word that yields an ADC throughput that is less than 20 Hz with chop enabled (SF ≥ 68 decimal). ADC CHOPPING The ADCs on the ADuC845/ADuC847/ADuC848 implement a chopping scheme whereby the ADC repeatedly reverses ...
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There is no penalty to the full-scale calibration in redoing the zero-scale calibration at the ...
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ADuC845/ADuC847/ADuC848 DATA OUTPUT CODING When the primary ADC is configured for unipolar operation, the output coding is natural (straight) binary with a zero differ- ential input voltage resulting in a code of 000...000, a midscale voltage resulting in a code ...
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TYPICAL PERFORMANCE CHARACTERISTICS 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 FREQUENCY (Hz) Figure 18. Filter Response, Chop On Decimal –10 –30 –50 –70 ...
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ADuC845/ADuC847/ADuC848 0 –20 –40 –60 –80 –100 –120 FREQUENCY (Hz) Figure 24. Chop On, Fadc = 16.6 Hz 52H 0 –20 –40 –60 –80 –100 –120 Figure 25. Chop On, Fadc = 16.6 Hz 52H, REJ60 ...
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FUNCTIONAL DESCRIPTION ADC SFR INTERFACE The ADCs are controlled and configured via a number of SFRs that are mentioned here and described in more detail in the following sections. Table 22. ADC SFR Interface Name Description ADCSTAT ADC Status Register. ...
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ADuC845/ADuC847/ADuC848 ADCSTAT (ADC STATUS REGISTER) This SFR reflects the status of both ADCs including data ready, calibration, and various (ADC-related) error and warning conditions including REFIN± reference detect and conversion overflow/underflow flags. SFR Address: D8H Power-On Default: 00H Bit Addressable: ...
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ADCMODE (ADC MODE REGISTER) Used to control the operational mode of both ADCs. SFR Address: D1H Power-On Default: 08H Bit Addressable: No Table 24. ADCMODE SFR Bit Designations Bit No. Name Description 7 ––– Not Implemented. Write Don’t Care. 6 ...
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ADuC845/ADuC847/ADuC848 Notes on the ADCMODE Register • Any change to the MD bits immediately resets both ADCs (auxiliary ADC only applicable to the ADuC845). A write to the MD2–MD0 bits with no change in contents is also treated as a ...
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ADC0CON1 (PRIMARY ADC CONTROL REGISTER) ADC0CON1 is used to configure the primary ADC for buffer, unipolar, or bipolar coding, and ADC range configuration. SFR Address: D2H Power-On Default: 07H Bit Addressable: No Table 25. ADC0CON1 SFR Bit Designations Bit No. ...
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ADuC845/ADuC847/ADuC848 ADC0CON2 (PRIMARY ADC CHANNEL SELECT REGISTER) ADC0CON2 is used to select a reference source and channel for the primary ADC. SFR Address: E6H Power-On Default: 00H Bit Addressable: No Table 26. ADC0CON2 SFR Bit Designations Bit No. Name Description ...
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ADC1CON (AUXILIARY ADC CONTROL REGISTER) (ADuC845 ONLY) ADC1CON is used to configure the auxiliary ADC for reference, channel selection, and unipolar or bipolar coding. The auxiliary ADC is available only on the ADuC845. SFR Address: D3H Power-On Default: 00H Bit ...
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ADuC845/ADuC847/ADuC848 SF (ADC SINC FILTER CONTROL REGISTER) The SF register is used to configure the decimation factor for the ADC, and therefore, has a direct influence on the ADC throughput rate. SFR Address: D4H Power-On Default: 45H Bit Addressable: No ...
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ICON (EXCITATION CURRENT SOURCES CONTROL REGISTER) The ICON register is used to configure the current sources and the burnout detection source. SFR Address: D5H Power-On Default: 00H Bit Addressable: No Table 30. Excitation Current Source SFR Bit Designations Bit No. ...
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ADuC845/ADuC847/ADuC848 NONVOLATILE FLASH/EE MEMORY OVERVIEW The ADuC845/ADuC847/ADuC848 incorporate Flash/EE memory technology on-chip to provide the user with nonvolatile, in-circuit reprogrammable code and data memory space. Like EEPROM, flash memory can be programmed in-system at the byte level, although it must ...
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ADI SPECIFICATION 100 YEARS MIN 55°C J 150 100 JUNCTION TEMPERATURE (°C) J Figure 27. Flash/EE Memory Data Retention FLASH/EE PROGRAM MEMORY The ADuC845/ADuC847/ADuC848 contain a ...
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ADuC845/ADuC847/ADuC848 USER DOWNLOAD MODE (ULOAD) Figure 28 shows that it is possible to use the 62 kbytes of Flash/EE program memory available to the user as one single block of memory. In this mode, all the Flash/EE memory is read-only ...
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USING FLASH/EE DATA MEMORY The 4 kbytes of Flash/EE data memory are configured as 1024 pages, each of 4 bytes. As with the other ADuC845/ADuC847/ ADuC848 peripherals, the interface to this memory space is via a group of registers mapped ...
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ADuC845/ADuC847/ADuC848 Example: Programming the Flash/EE Data Memory A user wants to program F3H into the second byte on Page 03H of the Flash/EE data memory space while preserving the other 3 bytes already in this page. A typical program of ...
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DAC CIRCUIT INFORMATION The ADuC845/ADuC847/ADuC848 incorporate a 12-bit, voltage output DAC on-chip. It has a rail-to-rail voltage output buffer capable of driving 10 kΩ/100 pF, and has two selectable ranges and ...
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ADuC845/ADuC847/ADuC848 Using the DAC The on-chip DAC architecture consists of a resistor string DAC followed by an output buffer amplifier, the functional equivalent of which is shown in Figure 33 REF R OUTPUT BUFFER R R HIGH-Z ...
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DAC LOADED WITH 0FFFH 2 1 DAC LOADED WITH 0000H SOURCE/SINK CURRENT (mA) Figure 36. Source and Sink Current Capability with V For larger loads, the current drive capability may not be sufficient. To increase the ...
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ADuC845/ADuC847/ADuC848 PWMCON PWM Control SFR SFR Address: AEH Power-On Default: 00H Bit Addressable: No Table 34. PWMCON PWM Control SFR Bit No. Name Description 7 ––– Not Implemented. Write Don’t Care PWM2, PWM1, PWM0 PMW Mode Selection. ...
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PWM Cycle Width High Byte (PWM1H) SFR Address: B4H Power-On Default: 00H Bit Addressable: No Table 37. PWM1H: PWM Cycle Width High Byte PWM1H.7 PWM1H.6 PWM1H R/W R/W R/W PWM Cycle Width Low Byte (PWM1L) SFR Address: ...
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ADuC845/ADuC847/ADuC848 Mode 3 (Twin 16-Bit PWM) In Mode 3, the PWM counter is fixed to count from 0 to 65536, giving a fixed 16-bit PWM. Operating from the 12.58 MHz core clock results in a PWM output rate of 192 ...
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Mode 5 (Dual 8-Bit PWM) In Mode 5, the duty cycle and the resolution of the PWM outputs are individually programmable. The maximum resolution of the PWM output is 8 bits. PWM COUNTERS Figure 43. PWM Mode 5 Mode 6 ...
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ADuC845/ADuC847/ADuC848 ON-CHIP PLL (PLLCON) The ADuC845/ADuC847/ADuC848 are intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple (384) of this to provide a stable 12.582912 MHz clock for the system. The core can operate at ...
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I C SERIAL INTERFACE The ADuC845/ADuC847/ADuC848 support a fully licensed serial interface. The I C interface is implemented as a full hardware slave and software master. SDATA (Pin 27 on the MQFP package and Pin ...
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ADuC845/ADuC847/ADuC848 2 I2CADD—I C Address Register 1 Function: Holds one of the I uC001 at http://www.analog.com/microconverter SFR Address: 9BH Power-On Default: 55H Bit Addressable I2CADD1—I C Address Register 2 Function: Same as the I2CADD. SFR Address: F2H Power-On ...
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Hardware Slave Mode After reset, the ADuC845/ADuC847/ADuC848 default to 2 hardware slave mode. The I C interface is enabled by clearing the SPE bit in SPICON. Slave mode is enabled by clearing the I2CM bit in I2CCON. The parts have ...
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ADuC845/ADuC847/ADuC848 SPI SERIAL INTERFACE The ADuC845/ADuC847/ADuC848 integrate a complete hardware serial peripheral interface (SPI) interface on-chip. SPI is an industry-standard synchronous serial interface that allows 8 bits of data to be synchronously transmitted and received simultaneously, that is, full duplex. ...
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SPICON—SPI Control Register SFR Address: F8H Power-On Default: 05H Bit Addressable: Yes Table 41. SPICON SFR Bit Designations Bit No. Name Description 7 ISPI SPI Interrupt Bit. Set by the MicroConverter at the end of each SPI transfer. Cleared directly ...
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ADuC845/ADuC847/ADuC848 USING THE SPI INTERFACE Depending on the configuration of the bits in the SPICON SFR shown in Table 41, the SPI interface transmits or receives data in a number of possible modes. Figure 46 shows all possible ADuC845/ADuC847/ADuC848 SPI ...
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DUAL DATA POINTERS The parts incorporate two data pointers. The second data pointer is a shadow data pointer and is selected via the data pointer control SFR (DPCON). DPCON features automatic hardware post-increment and post-decrement as well as an automatic ...
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ADuC845/ADuC847/ADuC848 POWER SUPPLY MONITOR The power supply monitor, once enabled, monitors the DV and AV supplies on the parts. It indicates when any of the DD supply pins drop below one of four user-selectable voltage trip points from 2.63 V ...
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WATCHDOG TIMER The watchdog timer generates a device reset or interrupt within a reasonable amount of time if the ADuC845/ADuC847/ ADuC848 enters an erroneous state, possibly due to a program- ming error or electrical noise. The watchdog function can be ...
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ADuC845/ADuC847/ADuC848 TIME INTERVAL COUNTER (TIC) A TIC is provided on-chip for counting longer intervals than the standard 8051 compatible timers can count. The TIC is capable of timeout intervals ranging from 1/128 second to 255 hours. Also, this counter is ...
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TIMECON—TIC Control Register SFR Address: A1H Power-On Default: 00H Bit Addressable: No Table 45. TIMECON SFR Bit Designations Bit No. Name Description 7 ---- Not Implemented. Write Don’t Care. 6 TFH Twenty-Four Hour Select Bit. Set by the user to ...
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ADuC845/ADuC847/ADuC848 INTVAL—User Timer Interval Select Register Function: User code writes the required time interval to this register. When the 8-bit interval counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) is set ...
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COMPATIBLE ON-CHIP PERIPHERALS This section gives a brief overview of the various secondary peripheral circuits that are available to the user on-chip. These features are mostly 8052 compatible (with a few additional features) and are controlled via standard 8052 ...
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ADuC845/ADuC847/ADuC848 P2.5 and P2.6 can also be used as PWM outputs, while P2.7 can act as an alternate PWM clock source. When selected as the PWM outputs, they overwrite anything written to P2.5 or P2.6. Table 47. Port 2 Alternate ...
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TIMERS/COUNTERS The ADuC845/ADuC847/ADuC848 have three 16-bit timer/ counters: Timer 0, Timer 1, and Timer 2. The timer/counter hardware is included on-chip to relieve the processor core of the overhead inherent in implementing timer/counter functionality in software. Each timer/counter consists of ...
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ADuC845/ADuC847/ADuC848 TCON—Timer/Counter 0 and 1 Control Register SFR Address: 88H Power-On Default: 00H Bit Addressable: Yes Table 51. TCON SFR Bit Designations Bit No. Name Description 7 TF1 Timer 1 Overflow Flag. Set by hardware on a Timer/Counter 1 overflow. ...
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Timer/Counter 0 and 1 Operating Modes This section describes the operating modes for Timer/Counters 0 and 1. Unless otherwise noted, these modes of operation are the same for both Timer 0 and Timer 1. Mode 0 (13-Bit Timer/Counter) Mode 0 ...
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ADuC845/ADuC847/ADuC848 T2CON—Timer/Counter 2 Control Register SFR Address: C8H Power-On Default: 00H Bit Addressable: Yes Table 52. T2CON SFR Bit Designations Bit No. Name Description 7 TF2 Timer 2 Overflow Flag. Set by hardware on a Timer 2 overflow. TF2 cannot ...
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Timer/Counter 2 Operating Modes The following sections describe the operating modes for Timer/Counter 2. The operating modes are selected by bits in the T2CON SFR as shown in Table 53. Table 53. T2CON Operating Modes RCLK (or) TCLK CAP2 TR2 ...
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ADuC845/ADuC847/ADuC848 UART SERIAL INTERFACE The serial port is full duplex, meaning that it can transmit and receive simultaneously also receive buffered, meaning that it can begin receiving a second byte before a previously received byte is read from ...
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Mode 0 (8-Bit Shift Register Mode) Mode 0 is selected by clearing both the SM0 and SM1 bits in the SFR SCON. Serial data enters and exits through RxD. TxD outputs the shift clock. Eight data bits are transmitted or ...
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ADuC845/ADuC847/ADuC848 Mode 3 (9-Bit UART with Variable Baud Rate) Mode 3 is selected by setting both SM0 and SM1. In this mode, the 8051 UART serial port operates in 9-bit mode with a variable baud rate determined by either Timer ...
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Timer 3 Generated Baud Rates The high integer dividers in a UART block mean that high speed baud rates are not always possible. Also, generating baud rates requires the exclusive use of a timer, rendering it unusable for other applications ...
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ADuC845/ADuC847/ADuC848 T3FD—Timer 3 Fractional Divider Register See Table 57 for values. SFR Address: 9DH Power-On Default: 00H Bit Addressable: No Table 56. T3FD SFR Bit Designations Bit No. Name Description 7 ---- Not Implemented. Write Don’t Care. 6 ---- Not ...
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INTERRUPT SYSTEM The ADuC845/ADuC847/ADuC848 provide nine interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three interrupt-related SFRs: Interrupt Enable Register IE IP Interrupt Priority Register IEIP2 Secondary Interrupt Enable Register ...
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ADuC845/ADuC847/ADuC848 IEIP2—Secondary Interrupt Enable Register SFR Address: A9H Power-On Default: A0H Bit Addressable: No Table 60. IEIP2 Bit Designations Bit No. Name Description 7 ---- Not Implemented. Write Don’t Care. 6 PTI Time Interval Counter Interrupt Priority Setting (1 = ...
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HARDWARE DESIGN CONSIDERATIONS This section outlines some of the key hardware design considerations that must be addressed when integrating the ADuC845/ADuC847/ADuC848 into any hardware system. EXTERNAL MEMORY INTERFACE In addition to their internal program and data memories, the parts can ...
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ADuC845/ADuC847/ADuC848 As an alternative to providing two separate power supplies, AV can be kept quiet by placing a small series resistor and/or DD ferrite bead between it and DV , and then decoupling AV DD separately to ground. An example ...
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SPI Interrupt If the SERIPD bit in the PCON SFR is set, an SPI interrupt, if enabled, wakes up the part from power-down mode. The CPU services the SPI interrupt. The RETI at the end of the ISR returns ...
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ADuC845/ADuC847/ADuC848 When using the LFCSP package recommended that the paddle underneath the chip be soldered to the board to provide maximum mechanical stability. However recommended that this paddle not be grounded but left floating. All results ...
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EXCITATION AV CURRENT RTD R REF 5.6kV RESET ACTIVE HIGH. RS232 INTERFACE* ADM3202 C1+ 0.1µF V+ C1– C2+ C2– 0.1µF V– T2OUT R2IN *EXTERNAL UART TRANSCEIVER INTEGRATED IN SYSTEM OR AS PART OF AN EXTERNAL DONGLE AS DESCRIBED IN ...
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ADuC845/ADuC847/ADuC848 Single-Pin Emulation Mode Built into the ADuC845/ADuC847/ADuC848 is a dedicated controller for single-pin in-circuit emulation (ICE). In this mode, emulation access is gained by connection to a single pin, the EA pin. Normally on the 8051 standard, this pin ...
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P1.6/I 1/AIN7 11 EXC 200mA/400mA AV EXCITATION ADuC845/ADuC847/ADuC848 DD CURRENT 0.1µF AGND 5 AGND 6 RTD REFIN– 7 REFIN REF 5.6kV P1.0/AIN1 56 P1.1/AIN2 P1.2/AIN3/REFIN2 AIN9 15 AIN10 16 ...
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ADuC845/ADuC847/ADuC848 QuickStart DEVELOPMENT SYSTEM The QuickStart Development System is an entry-level, low cost development tool suite supporting the ADuC8xx MicroConverter product family. The system consists of the following PC-based (Windows® compatible) hardware and software development tools: Hardware: Evaluation board and ...
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TIMING SPECIFICATIONS AC inputs during testing are driven at DV Logic 1 and V max for Logic 0 as shown in Figure 71. IL For timing purposes, a port pin is no longer floating when a 100 mV change from ...
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ADuC845/ADuC847/ADuC848 Table 65. EXTERNAL DATA MEMORY READ CYCLE Parameter t RD Pulse Width RLRH t Address Valid after ALE Low AVLL t Address Hold after ALE Low LLAX t RD Low to Valid Data In RLDV t Data and Address ...
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Table 66. EXTERNAL DATA MEMORY WRITE CYCLE Parameter t WR Pulse Width WLWH t Address Valid after ALE Low AVLL t Address Hold after ALE Low LLAX t ALE Low Low LLWL t Address Valid to ...
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ADuC845/ADuC847/ADuC848 2 Table 67 COMPATIBLE INTERFACE TIMING Parameter Parameter t SCLOCK Low Pulse Width L t SCLOCK High Pulse Width H t Start Condition Hold Time SHD t Data Setup Time DSU t Data Hold Time DHD t ...
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Table 68. SPI MASTER MODE TIMING (CPHA = 1) Parameter t SCLOCK Low Pulse Width SCLOCK High Pulse Width SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK Edge DSU ...
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ADuC845/ADuC847/ADuC848 Table 69. SPI MASTER MODE TIMING (CPHA = 0) Parameter t SCLOCK Low Pulse Width SL t SCLOCK High Pulse Width SH t Data Output Valid after SCLOCK Edge DAV t Data Output Setup before SCLOCK Edge DOSU t ...
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Table 70. SPI SLAVE MODE TIMING (CPHA = 1) Parameter SCLOCK Edge SS t SCLOCK Low Pulse Width SL t SCLOCK High Pulse Width SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup ...
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ADuC845/ADuC847/ADuC848 Table 71. SPI SLAVE MODE TIMING (CPHA = 0) Parameter SCLOCK Edge SS t SCLOCK Low Pulse Width SL t SCLOCK High Pulse Width SH t Data Output Valid after SCLOCK Edge DAV t Data Input ...
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Table 72. UART Timing (Shift Register Mode) Parameter TXLXL Serial Port Clock Cycle Time TQVXH Output Data Setup to Clock TDVXH Input Data Setup to Clock TXHDX Input Data Hold after Clock TXHQX Output Data Hold after Clock TxD (OUTPUT ...
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ADuC845/ADuC847/ADuC848 OUTLINE DIMENSIONS 10° 6° 2.10 2° 2.00 1.95 0.25 MAX VIEW A ROTATED 90° CCW PIN 1 INDICATOR 1.00 12° MAX 0.85 0.80 SEATING PLANE 1.03 2.45 0.88 MAX 0.73 39 SEATING 40 PLANE 7.80 REF 0.23 0.11 VIEW ...
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... ADuC847BS8-5 −40°C to +125°C ADuC847BS8-3 −40°C to +125°C ADuC847BCP62-5 −40°C to +85°C ADuC847BCP62-3 −40°C to +85°C ADuC847BCP8-5 −40°C to +85°C ADuC847BCP8-3 −40°C to +85°C ADuC848BS62-5 −40°C to +125°C ADuC848BS62-3 −40°C to +125°C ADuC848BS32-5 − ...
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ADuC845/ADuC847/ADuC848 NOTES Rev Page 106 of 108 ...
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NOTES ADuC845/ADuC847/ADuC848 Rev Page 107 of 108 ...
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ADuC845/ADuC847/ADuC848 NOTES 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, ...