ADUC847BCP8-5 AD [Analog Devices], ADUC847BCP8-5 Datasheet - Page 61

• Manufacturer Part Number: ADUC847BCP8-5
• Description: MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU
• Manufacturer: AD [Analog Devices]

I
The ADuC845/ADuC847/ADuC848 support a fully licensed
I
hardware slave and software master. SDATA (Pin 27 on the
MQFP package and Pin 29 on the CSP package) is the data I/O
pin. SCLK (Pin 26 on the MQFP package and Pin 28 on the CSP
package) is the serial interface clock for the SPI interface. The
I
function multiplexing. The I
ADuC845/ADuC847/ADuC848 also includes a second address
register (I2CADD1) at SFR Address F2H with a default power-
on value of 7FH. The I
and is not multiplexed with any other I/O functionality on the
chip. This means that the I
the same time.
Table 40. I2CCON SFR Bit Designations
Bit No.
7
6
5
4
3
2
1
0
2
2
2
C serial interface. The I
C interface on the parts is fully independent of all other pin/
C SERIAL INTERFACE
Name
MDO
MDE
MCO
MDI
I2CM
I2CRS
I2CTX
I2CI
2
Description
I
This data bit is used to implement a master I
the SDATA pin if the data output enable bit (MDE) is set.
I
Set by the user to enable the SDATA pin as an output (Tx).
Cleared by the user to enable the SDATA pin as an input (Rx).
I
This bit is used to implement the SCLK for a master I
the SCLK pin.
I
This data bit is used to implement a master I
this bit on an SCLK transition if the data output enable (MDE) bit is 0.
I
Set by the user to enable I
Cleared by the user to enable I
I
Set by the user to reset the I
Cleared by the user code for normal I
I
Set by the MicroConverter if the I
Cleared by the MicroConverter if the I
I
Set by the MicroConverter after a byte has been transmitted or received.
Cleared by the MicroConverter when the user code reads the I2CDAT SFR. I2CI should not be cleared by user code.
C interface is always available to the user
2
2
2
2
2
2
2
2
C Software Master Data Output Bit (master mode only).
C Software Output Enable Bit (master mode only).
C Software Master Clock Output Bit (master mode only).
C Software Master Data Input Bit (master mode only).
C Master/Slave Mode Bit.
C Reset Bit (slave mode only).
C Direction Transfer Bit (slave mode only).
C Interrupt Bit (slave mode only).
2
C interface is implemented as a full
2
C and SPI interfaces can be used at
2
C interface incorporated on the
2
C software master mode.
2
C interface.
2
C hardware slave mode.
2
C interface is transmitting.
2
2
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C operation.
C interface is receiving.
2
2
C transmitter interface in software. Data written to this bit is output on
C receiver interface in software. Data on the SDATA pin is latched into
Note that when using the I
they both use the same interrupt routine (Vector Address 3BH).
When an interrupt occurs from one of these, it is necessary to
interrogate each interface to see which one has triggered the ISR
request.
The four SFRs are used to control the I
described next.
I2CCON—I
SFR Address:
Power-On Default:
Bit Addressable:
2
C transmitter in software. Data written to this bit is output on
2
C Control Register
ADuC845/ADuC847/ADuC848
E8H
00H
Yes
2
C and SPI interfaces simultaneously,
2
C interface are