ADUC847BCP8-5 AD [Analog Devices], ADUC847BCP8-5 Datasheet - Page 24

• Manufacturer Part Number: ADUC847BCP8-5
• Description: MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU
• Manufacturer: AD [Analog Devices]

ADuC845/ADuC847/ADuC848
SPECIAL FUNCTION REGISTERS (SFRs)
The SFR space is mapped into the upper 128 bytes of internal
data memory space and accessed by direct addressing only. It
provides an interface between the CPU and all on-chip periph-
erals. A block diagram showing the programming model of the
ADuC845/ADuC847/ADuC848 via the SFR area is shown in
Figure 11.
All registers except the program counter (PC) and the four
general-purpose register banks reside in the SFR area. The SFR
registers include control, configuration, and data registers that
provide an interface between the CPU and all on-chip peripherals.
Accumulator SFR (ACC)
ACC is the accumulator register, which is used for math opera-
tions including addition, subtraction, integer multiplication and
division, and Boolean bit manipulations. The mnemonics for
accumulator-specific instructions usually refer to the accumulator
as A.
B SFR (B)
The B register is used with the accumulator for multiplication
and division operations. For other instructions, it can be treated
as a general-purpose scratch pad register.
FLASH/EE PROGRAM
REPROGRAMMABLE
256 BYTES RAM
2kBYTES XRAM
ELECTRICALLY
COMPATIBLE
NONVOLATILE
62-kBYTE
MEMORY
CORE
8051
Figure 11. Programming Model
FUNCTION
REGISTER
128-BYTE
SPECIAL
AREA
REPROGRAMMABLE
CURRENT SOURCES
FLASH/EE DATA
OTHER ON-CHIP
ELECTRICALLY
TEMPERATURE
NONVOLATILE
PERIPHERALS
12-BIT DAC
SERIAL I/O
MEMORY
4-kBYTE
SENSOR
Σ-∆ ADC
PWM
WDT
PSM
TIC
Rev. A | Page 24 of 108
Data Pointer (DPTR)
The data pointer is made up of three 8-bit registers: DPP (page
byte), DPH (high byte), and DPL (low byte). These provide
memory addresses for internal code and data memory access.
The DPTR can be manipulated as a 16-bit register (DPTR =
DPH, DPL), although INC DPTR instructions automatically
carry over to DPP, or as three independent 8-bit registers (DPP,
DPH, DPL).
The ADuC845/ADuC847/ADuC848 supports dual data
pointers. See the Dual Data Pointers section.
Stack Pointer (SP and SPH)
The SP SFR is the stack pointer, which is used to hold an
internal RAM address called the top of the stack. The SP register
is incremented before data is stored during PUSH and CALL
executions. Although the stack can reside anywhere in on-chip
RAM, the SP register is initialized to 07H after a reset. This
causes the stack to begin at location 08H.
As mentioned earlier, the parts offer an extended 11-bit stack
pointer. The 3 extra bits needed to make up the 11-bit stack
pointer are the 3 LSBs of the SPH byte located at B7H. To enable
the SPH SFR, the EXSP (CFG84x.7) bit must be set; otherwise,
the SPH SFR can be neither written to nor read from.
Program Status Word (PSW)
The PSW SFR contains several bits that reflect the current
status of the CPU as listed in Table 5.
SFR Address:
Power-On Default:
Bit Addressable:
Table 5. PSW SFR Bit Designations
Bit No.
7
6
5
4, 3
2
1
0
Name
CY
AC
F0
RS1, RS0
OV
F1
P
D0H
00H
Yes
Description
Carry Flag.
Auxiliary Carry Flag.
General-Purpose Flag.
Register Bank Select Bits.
RS1
0
0
1
1
Overflow Flag.
General-Purpose Flag.
Parity Bit.
RS0
0
1
0
1
Selected Bank
0
1
2
3