ADUC847BCP8-5 AD [Analog Devices], ADUC847BCP8-5 Datasheet - Page 31

• Manufacturer Part Number: ADUC847BCP8-5
• Description: MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU
• Manufacturer: AD [Analog Devices]

ADC Noise Performance with Chop Disabled (CHOP = 1)
Table 14, Table 15, Table 16, and Table 17 show the output rms
noise and output peak-to-peak resolution in bits (rounded to
the nearest 0.5 LSB) for some typical output update rates. The
numbers are typical and are generated at a differential input
voltage of 0 V and a common-mode voltage of 2.5 V. The output
update rate is selected via the SF7 to SF0 bits in the SF filter
register. Note that the peak-to-peak resolution figures represent
the resolution for which there is no code flicker within a 6-
sigma limit.
The output noise comes from two sources. The first source is
the electrical noise in the semiconductor devices (device noise)
used in the implementation of the modulator. The second
Table 14. ADuC845 and ADuC847 Typical Output RMS Noise (µV) vs. Input Range and Update Rate with Chop Disabled
SF Word
3
13
68
82
255
Table 15. ADuC845 and ADuC847 Typical Peak-to-Peak Resolution (Bits) vs. Input Range and Update Rate with Chop Disabled
SF Word
3
13
68
82
255
Table 16. ADuC848 Typical Output RMS Noise (µV) vs. Input Range and Update Rate with Chop Disabled
SF Word
3
13
69
82
255
Table 17. ADuC848 Typical Peak-to-Peak Resolution (Bits) vs. Input Range and Update Rate with Chop Disabled
SF Word
3
13
68
82
255
Data Update Rate
(Hz)
1365.33
315.08
59.36
49.95
16.06
Data Update
Rate (Hz)
1365.33
315.08
59.36
49.95
16.06
Data Update
Rate (Hz)
1365.33
315.08
59.36
49.95
16.06
Data Update
Rate (Hz)
1365.33
315.08
59.36
49.95
16.06
±20 mV
7.5
11.5
13
13
13.5
±20 mV
30.64
2.07
0.85
0.83
0.52
±20 mV
7.5
11.5
13
13
13.5
±20 mV
30.64
2.07
0.85
0.83
0.52
±40 mV
9
12.5
14
14
14.5
±40 mV
24.5
1.95
0.79
0.77
0.58
±40 mV
9
12.5
14
14
14.5
±40 mV
24.5
1.95
0.79
0.77
0.58
±80 mV
9
13.5
14.5
15
15.5
±80 mV
56.18
2.28
1.01
0.85
0.59
±80 mV
9
13.5
14.5
15
15.5
±80 mV
56.18
2.28
1.01
0.85
0.59
Rev. A | Page 31 of 108
±160 mV
9
14
15.5
16
16
±160 mV
100.47
3.24
0.99
0.77
0.48
±160 mV
9
14
15.5
16
16.5
±160 mV
100.47
3.24
0.99
0.77
0.48
source is quantization noise, which is added when the analog
input is converted to the digital domain. The device noise is at a
low level and is independent of frequency. The quantization
noise starts at an even lower level but rises rapidly with increasing
frequency to become the dominant noise source.
The numbers in the tables are given for the bipolar input ranges.
For the unipolar ranges, the rms noise numbers are the same as
the bipolar range, but the peak-to-peak resolution is based on
half the signal range, which effectively means losing 1 bit of
resolution. Typically, the performance of the ADC with chop
disabled shows a 0.5 LSB degradation over the performance
with chop enabled.
Input Range
Input Range
Input Range
Input Range
±320mV
9
13.5
16
16
16
±320 mV
248.39
8.22
0.79
0.91
0.52
±320 mV
9
13.5
17
16.5
17.5
±320 mV
248.39
8.22
0.79
0.91
0.52
ADuC845/ADuC847/ADuC848
±640mV
14
16
16
9
16
±640 mV
468.65
13.9
1.29
1.12
0.57
±640 mV
9
14
17
17.5
18.5
±640 mV
468.65
13.9
1.29
1.12
0.57
±1.28 V
9
14
16
16
16
±1.28 V
774.36
20.98
2.3
1.59
1.16
±1.28 V
9
14
17.5
18
18.5
±1.28 V
774.36
20.98
2.3
1.59
1.16
±2.56 V
1739.5
49.26
3.7
3.2
1.68
±2.56 V
9
14
18
18
19
±2.56 V
1739.5
49.26
3.7
3.2
1.68
±2.56 V
9
14
16
16
16