HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 263

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Timer Output Compare Control Register (TOCR)
TOCR is an 8-bit read/write register that selects the output compare output levels, enables output
compare output, and controls access to OCRA and OCRB.
TOCR is initialized to H'E0 upon reset and in standby mode, watch mode, subsleep mode, and
subactive mode.
Bits 7 to 5—Reserved Bits: Bit 7 to 5 are reserved; they are always read as 1, and cannot be
modified.
Bit 4—Output Compare Register Select (OCRS): OCRA and OCRB share the same address.
OCRS selects which register is accessed when this address is written or read. It does not affect the
operation of OCRA and OCRB.
Bit 4: OCRS
0
1
Bit 3—Output Enable A (OEA): Bit 3 enables or disables the timer output controlled by output
compare A.
Bit 3: OEA
0
1
Bit 2—Output Enable B (OEB): Bit 2 enables or disables the timer output controlled by output
compare B.
Bit 2: OEB
0
1
Bit
Initial value
Read/Write
Description
OCRA is selected
OCRB is selected
Description
Output compare A output is disabled
Output compare A output is enabled
Description
Output compare B output is disabled
Output compare B output is enabled
—
—
7
1
—
—
6
1
—
—
5
1
OCRS
R/W
4
0
OEA
R/W
3
0
OEB
R/W
2
0
OLVLA
R/W
1
0
(initial value)
(initial value)
(initial value)
OLVLB
R/W
0
0
255