74LCX573MTC_08 FAIRCHILD [Fairchild Semiconductor], 74LCX573MTC_08 Datasheet
74LCX573MTC_08
Related parts for 74LCX573MTC_08
74LCX573MTC_08 Summary of contents
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Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs Features 5V tolerant inputs and outputs 2.3V–3.6V V specifications provided CC 7 max 3.3V), 10µ Power down high impedance inputs and outputs ...
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Connection Diagrams Pin Assignments for SOIC, SOP, SSOP, TSSOP GND 10 Pad Assignments for ...
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Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure ...
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DC Electrical Characteristics Symbol Parameter V HIGH Level Input Voltage IH V LOW Level Input Voltage IL V HIGH Level Output OH Voltage V LOW Level Output OL Voltage I Input Leakage Current I I 3-STATE Output Leakage OZ I ...
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Dynamic Switching Characteristics Symbol Parameter V Quiet Output Dynamic Peak V OLP V Quiet Output Dynamic Valley V OLV Capacitance Symbol Parameter C Input Capacitance IN C Output Capacitance OUT C Power Dissipation Capacitance PD ©2006 Fairchild Semiconductor Corporation 74LCX573 ...
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AC Loading and Waveforms TEST SIGNAL Figure 1. AC Test Circuit (C DATA IN t pxx DATA OUT Waveform for Inverting and Non-Inverting Functions t W CONTROL IN CLOCK t PHL V OUTPUT mo Propagation Delay, Pulse Width and t ...
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Schematic Diagram (Generic for LCX Family) Input Stage Data ESD D2 N+/P– Input Stage Enable ESD D4 N+/P– ©2006 Fairchild Semiconductor Corporation 74LCX573 Rev. 1.6 ...
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Tape and Reel Specification Tape Format for DQFN Package Designator Section BQX Leader (Start End) Trailer (Hub End) Tape Dimensions inches (millimeters) Reel Dimensions inches (millimeters) Tape Size A 12mm 13.0 (330.0) 0.059 (1.50) 0.512 (13.00) 0.795 (20.20) 2.165 (55.00) ...
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Physical Dimensions 20 B 10.65 7.60 10.00 7.40 1 0.51 PIN ONE 0.35 INDICATOR 2.65 MAX 0.75 0.25 (R0.10) (R0.10) 8° 0° 1.27 0.40 SEATING PLANE (1.40) DETAIL A SCALE: 2:1 Figure 3. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC ...
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Physical Dimensions (Continued) Figure 4. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or ...
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Physical Dimensions (Continued) Figure 5. 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please ...
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Physical Dimensions (Continued) Figure 6. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or ...
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Physical Dimensions (Continued) Figure 7. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision ...
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TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. ® ACEx Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ ...