M36DR432A100ZA6C STMICROELECTRONICS [STMicroelectronics], M36DR432A100ZA6C Datasheet
M36DR432A100ZA6C
Related parts for M36DR432A100ZA6C
M36DR432A100ZA6C Summary of contents
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... Mbit (2Mb x16, Dual Bank, Page) Flash Memory and 4 Mbit (256K x16) SRAM, Multiple Memory Product FEATURES SUMMARY SUPPLY VOLTAGE – =1.65V to 2.2V DDF DDS – 12V for Fast Program (optional) PPF ACCESS TIME: 100,120ns LOW POWER CONSUMPTION ELECTRONIC SIGNATURE – Manufacturer Code: 20h – ...
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... M36DR432A, M36DR432B DESCRIPTION The M36DR432 is a multichip memory device con- taining a 32 Mbit boot block Flash memory and a 4 Mbit of SRAM. The device is offered in a Stacked LFBGA66 (0.8 mm pitch) package. The two components are distinguished by use with three chip enable inputs: EF for the Flash memory and, E1S and E2S for the SRAM ...
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Figure 3. LFBGA Connections (Top view through package A20 B A16 SSS E WPF F LBS G A18 A15 A14 A11 A13 ...
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... Figure 4. Functional Block Diagram RPF WPF A18-A20 A0-A17 E1S E2S GS WS UBS LBS 4/46 (1) Parameter (3) V DDF V PPF Flash Memory 32 Mbit (x16) V SSF V DDS SRAM 4 Mbit (x16) V SSS Value Unit – °C –40 to 125 °C –55 to 150 °C (4) V –0 0.3 DD – ...
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... IL PLPH en, if the memory is in Read, Erase Suspend Read or Standby, it will output new valid data in t after the rising edge of RPF. If the memory is in Erase or Program modes, the operation will be aborted and the reset recovery will take a maxi- mum of t Power Down (when enabled rising edge of RPF ...
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M36DR432A, M36DR432B Table 3. Main Operation Modes Operation Mode Read Write Block Locking V Standby Reset X X ...
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... EF, WF and GF signals do not start a write cycle. Dual Bank Operations. The Dual Bank allows to read data from one bank of memory while a pro- gram or erase operation is in progress in the other bank of the memory. Read and Write cycles can be initiated for simultaneous operations in different banks without any delay ...
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M36DR432A, M36DR432B Table 4. Bank Size and Sectorization Bank A Bank B Table 5. Bank A, Top Boot Block Addresses M36DR432A Size # Address Range (KWord 1FF000h-1FFFFFh 1 4 1FE000h-1FEFFFh 2 4 1FD000h-1FDFFFh 3 4 1FC000h-1FCFFFh 4 4 ...
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Table 7. Bank B, Bottom Boot Block Addresses M36DR432B Size # Address Range (KWord 1F8000h-1FFFFFh 54 32 1F0000h-1F7FFFh 53 32 1E8000h-1EFFFFh 52 32 1E0000h-1E7FFFh 51 32 1D8000h-1DFFFFh 50 32 1D0000h-1D7FFFh 49 32 1C8000h-1CFFFFh 48 32 1C0000h-1C7FFFh 47 32 ...
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M36DR432A, M36DR432B Table 9. User Bus Operations Operation EF Write V V Output Disable V Standby Reset / Power Down X V Block Locking Note Don't care. Table 10. Read Electronic Signature (AS and Read CFI instructions) ...
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... Coded Sequence before the Erase confirm command on the sixth cycle. Any combination of blocks of the same memory bank can be erased. Erasure of a memory block may be suspended, in order to read data from another block or to pro- gram data in another block, and then resumed. ...
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... Exit Bypass Mode (XBY) Instruction. This struction uses two write cycles. The first inputs to the memory the command 90h and the second in- puts the Exit Bypass mode confirm (00h). After the XBY instruction, the device resets to Read Memo- ry Array mode. ...
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... Cod- ed cycles. All blocks must belong to the same bank of memory new block belonging to the other bank is given, the operation is aborted. The erase will start after an erase timeout period of 100µs. Thus, additional Erase Confirm commands for other blocks must be given within this delay ...
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... Cyc. 2nd Cyc. (3) X Addr. Read Memory Array until a new write cycle is initiated. Data F0h Addr. 555h 2AAh Data AAh 55h Addr. 55h Read CFI data until a new write cycle is initiated. Data 98h Addr ...
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Mne. Instr. Cyc. Exit Bypass XBY 2 Mode Program in PGBY 2 Bypass Mode Double Word DPGBY Program in 3 Bypass Mode BP Block Protect 4 BU Block Unprotect 1 BL Block Lock 4 BE Block Erase 6+ BKE Bank ...
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... Error Bit (DQ5). This bit is set to '1' by the P/E.C. when there is a failure of programming or block erase, that results in invalid data in the memory block. In case of an error in block erase or pro- gram, the block in which the error occurred or to which the programmed data belongs, must be dis- carded ...
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Table 17. Status Register Bits DQ Name Logic Level '1' '0' Data 7 Polling DQ DQ '-1-0-1-0-1-0-1 Toggle Bit '-1-1-1-1-1-1-1-' '1' 5 Error Bit '0' 4 Reserved '1' Erase Time 3 Bit '0' '-1-0-1-0-1-0-1-' 2 Toggle Bit 1 ...
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... PLQ7V content is no longer valid (see Reset/Power Down input description). 18/46 Power Up The memory Command Interface is reset on Pow Read Array. Either must be tied to V during Power Up to allow maximum security IH and the possibility to write a command on the first rising edge of WF ...
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... A Alternate Algorithm-specific Extended Query table Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections detailed in Tables 19, 20 and 21. Query data are always presented on the lowest order data outputs. Table 19. CFI Query Identification String ...
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M36DR432A, M36DR432B Table 20. CFI Query System Interface Information Offset Data V Logic Supply Minimum Program/Erase or Write voltage CCF 1Bh 0017h V Logic Supply Maximum Program/Erase or Write voltage CCF 1Ch 0022h V [Programming] Supply Minimum Program/Erase voltage PPF ...
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Table 21. Device Geometry Definition Offset Word Data Mode 27h 0016h Device Size = 2 28h 0001h Flash Device Interface Code description: Asynchronous x16 29h 0000h 2Ah 0000h Maximum number of bytes in multi-byte program or page = 2 2Bh ...
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M36DR432A, M36DR432B SRAM COMPONENT Device Operations The following operations can be performed using the appropriate bus cycles: Read Array, Write Ar- ray, Output Disable, Power Down (see Table 3). Read. Read operations are used to output the contents of the ...
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Table 22. AC Measurement Conditions Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages Figure 5. AC Measurement Waveform Note: V means DDF DDS Table 23. Device Capacitance ...
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M36DR432A, M36DR432B Table 24. DC Characteristics (T = –40 to 85° DDF DDS Symbol Parameter Device Input Leakage Flash & Current SRAM Output Leakage Flash & Current SRAM Flash V Standby DD ...
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Symbol Parameter Device Program Voltage V (Program or Flash PPL Erase operations) Program Voltage V (Program or Flash PPH Erase operations) Program Voltage V (Program and Flash PPLK Erase lock-out) V Supply DDF Voltage (Program V Flash LKO and Erase ...
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M36DR432A, M36DR432B Figure 7. Flash Read AC Waveforms 26/46 ...
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Figure 8. Flash Page Read AC Waveforms M36DR432A, M36DR432B 27/46 ...
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M36DR432A, M36DR432B Table 26. Flash Write AC Characteristics, Write Enable Controlled (T = – ° 1.65V to 2.2V A DDF Symbol Alt t t Address Valid to Next Address Valid AVAV Address Valid ...
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Table 27. Flash Write AC Characteristics, Chip Enable Controlled (T = – ° 1.65V to 2.2V) A DDF Symbol Alt t t Address Valid to Next Address Valid AVAV Address Valid to Chip ...
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M36DR432A, M36DR432B Table 28. Flash Read and Write AC Characteristics, RPF Related (T = –40 to 85° 1.65V to 2.2V) A DDF Symbol Alt RPF High to Data Valid (Read t PHQ7V1 Mode) RPF High to Data Valid ...
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Table 29. Flash Program, Erase Times and Program, Erase Endurance Cycles (T = –40 to 85° 1.65V to 2.2V DDF Parameter Parameter Block (4 KWord) Erase (Preprogrammed) Main Block (32 KWord) Erase (Preprogrammed) Bank Erase (Preprogrammed, ...
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M36DR432A, M36DR432B Figure 12. Flash Data Polling DQ7 AC Waveforms 32/46 ...
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Figure 13. Flash Data Toggle DQ6, DQ2 AC Waveforms M36DR432A, M36DR432B 33/46 ...
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M36DR432A, M36DR432B Figure 14. Flash Data Polling Flowchart START READ DQ5 & DQ7 at VALID ADDRESS DQ7 YES = DATA NO NO DQ5 = 1 YES READ DQ7 DQ7 YES = DATA NO FAIL 34/46 Figure 15. Flash Data Toggle ...
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Table 31. SRAM Read AC Characteristics (T = –40 to 85° 1.65V to 2.2V) A DDS Symbol Alt t t Read Cycle Time AVAV Address Valid to Output Valid AVQV Address Transition ...
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M36DR432A, M36DR432B Figure 17. SRAM Read AC Waveforms, E1S, E2S or GS Controlled A0-A17 E1S E2S UBS, LBS GS DQ0-DQ15 Note: Write Enable (WS) = High. Figure 18. SRAM Standby AC Waveforms E1S E2S I DD 36/46 tAVAV VALID tAVQV ...
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Table 32. SRAM Write AC Characteristics (T = –40 to 85° 1.65V to 2.2V) A DDS Symbol Alt t t Write Cycle Time AVAV WC (1) t Address Valid to Chip Enable 1 Low t AVE1L AS (1) ...
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M36DR432A, M36DR432B Figure 19. SRAM Write AC Waveforms, WS Controlled with GS Low A0-A17 tAVE1L E1S E2S UBS, LBS WS DQ0-DQ15 Note: Output Enable (GS) = Low. Figure 20. SRAM Write AC Waveforms, WS Controlled with GS High A0-A17 tAVE1L ...
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Figure 21. SRAM Write Cycle Waveform, UBS and LBS Controlled A0-A17 E1S E2S tAVWL UBS, LBS WS DQ0-DQ15 Figure 22. SRAM Write AC Waveforms, E1S Controlled A0-A17 tAVE1L E1S E2S UBS, LBS tAVWL WS DQ0-DQ15 Note: Output Enable (GS) = ...
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M36DR432A, M36DR432B Table 33. SRAM Low V Data Retention Characteristics CCS (T = –40 to 85° 1.65V to 2.2V) A DDS Symbol Parameter I Supply Current (Data Retention) DDDR V Supply Voltage (Data Retention Chip Disable ...
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... ZA = LFBGA66: 0.8mm pitch Temperature Range 6 = –40 to 85°C Option T = Tape & Reel packing C = Cypress’s SRAM Devices are shipped from the factory with the memory content bits erased to ’1’. Table 35. Daisy Chain Ordering Scheme Example: Device Type M36DR432 Daisy Chain -ZA = LFBGA66: 0 ...
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M36DR432A, M36DR432B Table 36. Revision History Date Version 24-May-2001 -01 19-Nov-2001 -02 42/46 Revision Details First Issue LFBGA66 mechanical data updated (Table 37) ...
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Table 37. Stacked LFBGA66 - ball array, 0.8 mm pitch, Package Mechanical Data Symbol Typ 0.400 D 12.000 D1 5.600 D2 8.800 ddd E 8.000 E1 5.600 e 0.800 FD 1.600 FE 1.200 ...
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M36DR432A, M36DR432B Figure 26. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package 44/ AI90251 ...
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Figure 27. Stacked LFBGA66 Daisy Chain - PCB Connections proposal (Top view through package) START POINT # M36DR432A, M36DR432B END POINT # ...
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M36DR432A, M36DR432B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from ...