M36DR432A100ZA6C STMICROELECTRONICS [STMicroelectronics], M36DR432A100ZA6C Datasheet - Page 22

• Manufacturer Part Number: M36DR432A100ZA6C
• Description: 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M36DR432A, M36DR432B
SRAM COMPONENT
Device Operations
The following operations can be performed using
the appropriate bus cycles: Read Array, Write Ar-
ray, Output Disable, Power Down (see Table 3).
Read. Read operations are used to output the
contents of the SRAM Array. The SRAM is in Read
mode whenever Write Enable (WS) is at V
Output Enable (GS) at V
(E1S and E2S) and UBS, LBS combinations are
asserted.
Valid data will be available at the output pins within
t
Low, E1S is Low and E2S is High. If Chip Enable
or Output Enable access times are not met, data
access will be measured from the limiting parame-
ter (t
dress. Data out may be indeterminate at t
t
id at t
Write. Write operations are used to write data in
the SRAM. The SRAM is in Write mode whenever
the WS and E1S pins are at V
Either the Chip Enable inputs (E1S and E2S) or
the Write Enable input (WS) must be de-asserted
during address transitions for subsequent write cy-
cles. Write begins with the concurrence of both
Chip Enables being active with WS at V
begins at the latest transition among E1S going to
V
fore, address setup time is referenced to Write En-
able and both Chip Enables as t
t
22/46
AVQV
E2HQX
AVE2H
IL
, E2S going to V
E1LQV
after the last stable address, providing GS is
AVQV
respectively, and is determined by the latter
and t
, t
GLQX
(see Table 31, Figures 16 and 17).
E2HQV
, but data lines will always be val-
, or t
IH
and WS going to V
GLQV
IL
, and both Chip Enables
) rather than the ad-
IL
, with E2S at V
AVWL
, t
IL
AVE1L
IL
. A Write
. There-
IH
E1LQX
with
and
IH
,
.
occurring edge. The Write cycle can be terminated
by the rising edge of E1S, the rising edge of WS or
the falling edge of E2S, whichever occurs first.
If the Output is enabled (E1S=V
GS=V
impedance within t
must be taken to avoid bus contention in this type
of operation. Data input must be valid for t
before the rising edge of Write Enable, or for
t
before the falling edge of E2S, whichever occurs
first, and remain valid for t
(see Table 32, Figure 19, 21, 23).
Standby/Power-Down. The SRAM chip has a
Chip Enable power-down feature which invokes
an automatic standby mode (see Table 31, Figure
18) whenever either Chip Enable is de-asserted
(E1S=V
Data Retention
The SRAM data retention performances as V
go down to V
ure 23, 24. In E1S controlled data retention mode,
minimum standby current mode is entered when
E1S
E2S
tion mode, minimum standby current mode is en-
tered when E2S
Output Disable. The data outputs are high im-
pedance when the Output Enable (GS) is at V
with Write Enable (WS) at V
DVE1H
IL
V
V
before the rising edge of E1S or for t
), then WS will return the outputs to high
IH
CCS
CCS
or E2S=V
– 0.2V
– 0.2V. In E2S controlled data reten-
DR
are described in Table 33 and Fig-
0.2V.
WLQZ
IL
).
and
of its falling edge. Care
WHDX
IH
.
E2S
, t
IL
E1HAX
, E2S=V
0.2V
or t
IH
DVE2L
DVWH
E2LAX
CCS
and
or
IH