M36DR432A100ZA6C STMICROELECTRONICS [STMicroelectronics], M36DR432A100ZA6C Datasheet - Page 15

• Manufacturer Part Number: M36DR432A100ZA6C
• Description: 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Note: 1. Commands not interpreted in this table will default to read array mode.
DPGBY
PGBY
Mne.
XBY
BKE
BP
BU
BE
ES
ER
BL
2. For Coded cycles address inputs A11-A20 are don't care.
3. X = Don't Care.
4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the com-
5. During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.
6. Program Address 1 and Program Address 2 must be consecutive addresses differing only for address bit A0.
7. High voltage on V
mand cycles.
Exit Bypass
Mode
Program in
Bypass Mode
Double Word
Program in
Bypass Mode
Block Protect
Block Unprotect
Block Lock
Block Erase
Bank Erase
Erase Suspend
Erase Resume
Instr.
PPF
(11.4V to 12.6V) is required for the proper execution of the Double Word Program instruction.
Cyc.
6+
2
2
3
4
1
4
6
1
1
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
(3)
1st Cyc.
Address Read Data Polling or Toggle Bits until Erase completes or
555h
555h
555h
555h
555h
Bank
AAh
AAh
AAh
AAh
AAh
A0h
B0h
90h
40h
30h
X
X
X
X
Read until Toggle stops, then read all the data needed
from any Blocks not being erased then Resume Erase.
Erase is suspended another time
Address 1
2nd Cyc.
Program
Program
Program
Program
Address Read Data Polling or Toggle Bit until Program
Data 1
2AAh
2AAh
2AAh
2AAh
2AAh
Data
00h
55h
55h
55h
55h
55h
X
completes.
Address 2
3rd Cyc.
Program
Program
Data 2
555h
555h
555h
555h
555h
60h
60h
60h
80h
80h
M36DR432A, M36DR432B
4th Cyc.
Address
Address
Address
Block
Block
Block
555h
555h
D0h
AAh
AAh
2Fh
01h
Note 6, 7
5th Cyc.
2AAh
2AAh
55h
55h
6th Cyc.
Address
Address
Block
Bank
30h
10h
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