FDG6301N_09 FAIRCHILD [Fairchild Semiconductor], FDG6301N_09 Datasheet
FDG6301N_09
Manufacturer Part Number
FDG6301N_09
Description
Dual N-Channel, Digital FET
Manufacturer
FAIRCHILD [Fairchild Semiconductor]
Datasheet
1.FDG6301N_09.pdf
(5 pages)
©2009 Fairchild Semiconductor Corporation
FDG6301N_F085 Rev. A
Symbol
V
V
I
P
T
ESD
THERMAL CHARACTERISTICS
R
Absolute Maximum Ratings
D
FDG6301N_F085
Dual N-Channel, Digital FET
J
*
DSS
GSS
D
These dual N-Channel logic level enhancement mode
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance. This device has been
designed especially for low voltage applications as a
replacement for bipolar digital transistors and small
signal MOSFETs.
General Description
,T
JA
Units inside the carrier can be of either orientation and will not affect the functionality of the device.
The pinouts are symmetrical; pin 1 and 4 are interchangeable.
STG
SC70-6
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain/Output Current
Maximum Power Dissipation
Operating and Storage Temperature Range
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model(100 pF / 1500 )
Thermal Resistance, Junction-to-Ambient
SC70-6
D1
G2
SOT-23
S2
- Continuous
- Pulsed
S1
T
G1
A
= 25°C unless otherwise noted
SuperSOT
D2
(Note 1)
TM
-6
Features
1
Qualified to AEC Q101
RoHS Compliant
SuperSOT
25 V, 0.22 A continuous, 0.65 A peak.
Very low level gate drive requirements allowing direct
operation in 3 V circuits (V
Gate-Source Zener for ESD ruggedness
(>6kV Human Body Model).
Compact industry standard SC70-6 surface mount
package.
TM
-8
R
R
FDG6301N_F085
DS(ON)
DS(ON)
1 or 4
2 or 5
3 or 6
-55 to 150
0.22
0.65
415
6.0
0.3
25
*
= 4
= 5
8
SO-8
GS(th)
@ V
@ V
< 1.5 V).
GS
GS
= 4.5 V,
= 2.7 V.
www.fairchildsemi.com
March 2009
SOT-223
4 or 1
6 or 3
5 or 2
*
°C/W
Units
°C
kV
W
V
V
A
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FDG6301N_09 Summary of contents
Page 1
FDG6301N_F085 Dual N-Channel, Digital FET General Description These dual N-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This ...
Page 2
Electrical Characteristics Symbol Parameter OFF CHARACTERISTICS BV Drain-Source Breakdown Voltage DSS Breakdown Voltage Temp. Coefficient DSS J I Zero Gate Voltage Drain Current DSS I Gate - Body Leakage Current GSS ON CHARACTERISTICS (Note 2) V Gate ...
Page 3
Typical Electrical Characteristics 0.5 V =4.5V GS 3.5V 0.4 3.0V 2.7V 0.3 2.5V 0.2 0 DRAIN-SOURCE VOLTAGE (V) DS Figure 1. On-Region Characteristics . 1 0.22A D 1 4.5V ...
Page 4
Typical Electrical Characteristics 0.22A 0.1 0.2 0 GATE CHARGE (nC) g Figure 7. Gate Charge Characteristics. 1 0.3 0 4.5V GS ...
Page 5
TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. Build it Now™ CorePLUS™ CorePOWER™ CROSSVOLT™ CTL™ Current ...