AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 154

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Power Management Controller (PMC)
Description
Master Clock
Controller
Processor Clock
Controller
154
AT91SAM7S32 Preliminary
The Power Management Controller (PMC) optimizes power consumption by controlling all
system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the
peripherals and the ARM Processor.
The Power Management Controller provides the following clocks:
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•
•
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The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK
is the clock provided to all the peripherals and the memory controller.
The Master Clock is selected from one of the clocks provided by the Clock Generator. Select-
ing the Slow Clock provides a Slow Clock signal to the whole device. Selecting the Main Clock
saves power consumption of the PLL.
The Master Clock Controller is made up of a clock selector and a prescaler.
The Master Clock selection is made by writing the CSS field (Clock Source Selection) in
PMC_MCKR (Master Clock Register). The prescaler supports the division by a power of 2 of
the selected clock between 1 and 64. The PRES field in PMC_MCKR programs the prescaler.
Each time PMC_MCKR is written to define a new Master Clock, the MCKRDY bit is cleared in
PMC_SR. It reads 0 until the Master Clock is established. Then, the MCKRDY bit is set and
can trigger an interrupt to the processor. This feature is useful when switching from a high-
speed clock to a lower one to inform the software when the change is actually done.
Figure 57. Master Clock Controller
The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle
Mode. The Processor Clock can be enabled and disabled by writing the System Clock Enable
(PMC_SCER) and System Clock Disable Registers (PMC_SCDR). The status of this clock (at
least for debug purpose) can be read in the System Clock Status Register (PMC_SCSR).
MCK, the Master Clock, programmable from a few hundred Hz to the maximum operating
frequency of the device. It is available to the modules running permanently, such as the
AIC and the Memory Controller.
Processor Clock (PCK), switched off when entering processor in idle mode.
Peripheral Clocks, typically MCK, provided to the embedded peripherals (USART, SSC,
SPI, TWI, TC, MCI, etc.) and independently controllable. In order to reduce the number of
clock names in a product, the Peripheral Clocks are named MCK in the product datasheet.
Programmable Clock Outputs can be selected from the clocks provided by the clock
generator and driven on the PCKx pins.
MAINCK
PLLCK
SLCK
PMC_MCKR
CSS
PMC_MCKR
Master Clock
Prescaler
PRES
MCK
To the Processor
Clock Controller (PCK)
6071A–ATARM–28-Oct-04