AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 284

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Protocol T = 0
Figure 119. T = 0 Protocol without Parity Error
Figure 120. T = 0 Protocol with Parity Error
Receive Error Counter
Receive NACK Inhibit
284
Baud Rate
Baud Rate
Clock
I/O
AT91SAM7S32 Preliminary
Clock
RXD
Start
Bit
Start
Bit
D0
The USART cannot operate concurrently in both receiver and transmitter modes as the com-
munication is unidirectional at a time. It has to be configured according to the required mode
by enabling or disabling either the receiver or the transmitter as desired. Enabling both the
receiver and the transmitter at the same time in ISO7816 mode may lead to unpredictable
results.
The ISO7816 specification defines an inverse transmission format. Data bits of the character
must be transmitted on the I/O line at their negative value. The USART does not support this
format and the user has to perform an exclusive OR on the data before writing it in the Trans-
mit Holding Register (US_THR) or after reading it in the Receive Holding Register (US_RHR).
In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one
guard time, which lasts two bit times. The transmitter shifts out the bits and does not drive the
I/O line during the guard time.
If no parity error is detected, the I/O line remains at 1 during the guard time and the transmitter
can continue with the transmission of the next character, as shown in Figure 119.
If a parity error is detected by the receiver, it drives the I/O line at 0 during the guard time, as
shown in Figure 120. This error bit is also named NACK, for Non Acknowledge. In this case,
the character lasts 1 bit time more, as the guard time length is the same and is added to the
error bit time which lasts 1 bit time.
When the USART is the receiver and it detects an error, it does not load the erroneous charac-
ter in the Receive Holding Register (US_RHR). It appropriately sets the PARE bit in the Status
Register (US_SR) so that the software can handle the error.
The USART receiver also records the total number of errors. This can be read in the Number
of Error (US_NER) register. The NB_ERRORS field can record up to 255 errors. Reading
US_NER automatically clears the NB_ERRORS field.
The USART can also be configured to inhibit an error. This can be achieved by setting the
INACK bit in the Mode Register (US_MR). If INACK is at 1, no error signal is driven on the I/O
line even if a parity bit is detected, but the INACK bit is set in the Status Register (US_SR).
The INACK bit can be cleared by writing the Control Register (US_CR) with the RSTNACK bit
at 1.
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
Parity
Bit
Parity
Bit
Time 1
Guard
Time 1
Guard
Error
Time 2
Guard
Time 2
Guard
Next
Start
Bit
Start
6071A–ATARM–28-Oct-04
Bit
Repetition
D0
D1