AT32UC3L064_1 ATMEL [ATMEL Corporation], AT32UC3L064_1 Datasheet - Page 191

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AT32UC3L064_1

Manufacturer Part Number
AT32UC3L064_1
Description
AVR32 32-bit Microcontroller
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
14.5.2
14.5.3
32099A–AVR32–06/09
32KHz oscillator (OSC32K) operation
DFLL operation
Figure 14-1. Oscillator connections.
he 32KHz oscillator operates as described for the oscillator above. The 32KHz oscillator is used
as source clock for the Asynchronous Timer and the Watchdog Timer. The 32KHz oscillator can
be used as source for the generic clocks, as described in
The oscillator is disabled by default, but can be enabled by writing OSC32EN in OSCCTRL32.
The oscillator is an ultra-low power design and remains enabled in all sleep modes.
While the 32 KHz oscillator is disabled, the XIN32 and XOUT32 pins are available as general
purpose I/Os. When the oscillator is configured to work with an external clock (MODE field in
OSCCTRL32 register), the external clock must be connected to XIN32 while the XOUT32 pin
can be used as a general purpose I/O.
The startup time of the 32KHz oscillator can be set in the OSCCTRL32, after which OSC32RDY
in PCLKSR is set. An interrupt can be generated on a zero to one transition of OSC32RDY.
As a crystal oscillator usually requires a very long startup time (up to 1 second), the 32 KHz
oscillator will keep running across resets, except Power-On-Reset.
The 32 KHz oscillator also has a 1 KHz output. This is enabled by writing to EN1K bit in
OSCCTRL32 register. If the 32KHz output clock is not needed when 1K is enabled, this can be
disabled by writing zero to EN32K in OSCCTRL32 register. EN32K is set to one after reset.
The 32KHz oscillator has two possible set of pins. To select between them write to the PINSEL
bit in OSCCTRL32 register.
The 32KHz oscillator is not controlled by the sleep controller, and will run in all sleep modes if
enabled.
The device contains one Digital Frequency Locked Loop (DFLL). This is disabled by default, but
can be enabled to provide a high frequency source clock for synchronous and generic clocks.
The DFLL has a very short startup time and supports high frequency multiplication without the jit-
ter associated with a PLL.
Features:
• Internal oscillator with no external components.
XOUT
XIN
C
“Generic clocks” on page
C
2
1
AT32UC3L
196.
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