AT32UC3L064_1 ATMEL [ATMEL Corporation], AT32UC3L064_1 Datasheet - Page 41

• Manufacturer Part Number: AT32UC3L064_1
• Description: AVR32 32-bit Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

7.3.4
7.4
7.4.1
7.4.2
7.4.3
7.4.4
32099A–AVR32–06/09
Functional Description
Debug Operation
Bus Interfaces
Memory Organization
User Page
Read Operations
When an external debugger forces the CPU into debug mode, the FLASHCDW continues nor-
mal operation. If the FLASHCDW is configured in a way that requires it to be periodically
serviced by the CPU through interrupts or similar, improper operation or data loss may result
during debugging.
The FLASHCDW has two bus interfaces, one High Speed Bus (HSB) interface for reads from
the flash memory and writes to the page buffer, and one Peripheral Bus (PB) interface for issu-
ing commands and reading status from the controller.
The flash memory is divided into a set of pages. A page is the basic unit addressed when pro-
gramming the flash. A page consists of several words. The pages are grouped into 16 regions
of equal size. Each of these regions can be locked by a dedicated fuse bit, protecting it from
accidental modification.
The User page is an additional page, outside the regular flash array, that can be used to store
various data, such as calibration data and serial numbers. This page is not erased by regular
chip erase. The User page can only be written and erased by a special set of commands.
Read accesses to the User page are performed just as any other read accesses to the flash.
The address map of the User page is given in
The on-chip flash memory is typically used for storing instructions to be executed by the CPU.
The CPU will address instructions using the HSB bus, and the FLASHCDW will access the
flash memory and return the addressed 32-bit word.
In systems where the HSB clock period is slower than the access time of the flash memory,
the FLASHCDW can operate in 0 wait state mode, and output one 32-bit word on the bus per
clock cycle. If the clock frequency allows, the user should use 0 wait state mode, because this
gives the highest performance as no stall cycles are encountered.
The FLASHCDW can also operate in systems where the HSB bus clock period is faster than
the access speed of the flash memory. Wait state support and a read granularity of 64 bits
ensure efficiency in such systems.
Performance for systems with high clock frequency is increased since the internal read word
width of the flash memory is 64 bits. When a 32-bit word is to be addressed, the word itself
• p pages (FLASH_P)
• 256 bytes in each page and in the page buffer (FLASH_W)
• pw bytes in total (FLASH_PW)
• f general-purpose fuse bits (FLASH_F), used as region lock bits and for other device-
• 1 security fuse bit
• 1 User page
specific purposes
Figure 7-1 on page
43.
AT32UC3L
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