AT32UC3L064_1 ATMEL [ATMEL Corporation], AT32UC3L064_1 Datasheet - Page 550

• Manufacturer Part Number: AT32UC3L064_1
• Description: AVR32 32-bit Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

24.6.4
24.6.5
24.6.5.1
32099A–AVR32–06/09
Duty Cycle and Waveform Properties
Updating Duty Cycle Values
Interlinked Single Value PWM Operation
When writing a one to CR.TCLR, the timebase counter and the spread spectrum counter are
reset at their lower limit values and the effective top value of the timebase counter will also be
reset.
Each PWM channel has its own duty cycle value (DCV) which is write-only and cannot be read
out. The duty cycle value can be changed in two approaches as described in Section24.6.5.
When the duty cycle value is zero, the PWM output is zero. Otherwise, the PWM output is set
when the timebase counter is zero, and cleared when the timebase counter reaches the duty
cycle value. This is summarized as:
Note that when increasing the duty cycle value for one channel from 0 to 1, the number of GCLK
cycles when the PWM waveform is high will jump from 0 to 2. When incrementing the duty cycle
value by one for any other values, the number of GCLK cycle when the waveform is high will
increase by one. This is summarized in
Table 24-2.
Every other output PWM waveform toggles on the negative edge of the GCLK instead of the
positive edge. This is to avoid too many I/O toggling simultaneously on the output I/O lines.
The PWM channels can be interlinked to allow multiple channels to be updated simultaneously
with the same duty cycle value. This value must be written to the Interlinked Single Value Duty
(ISDUTY) register. Each channel has a corresponding enabling bit in the Interlinked Single
Value Channel Set (ISCHSET) register(s). When a bit is written to one in the ISCHSET register,
the duty cycle register for the corresponding channel will be updated with the value stored in the
ISDUTY register. It can only be updated when the READY bit in the Status Register
(SR.READY) is one, indicating that the PWMA is ready for writing.
shows the writing procedure. It is thus possible to update the duty cycle values for up to 32 PWM
channels within one ISCHSET register at a time.
Duty Cycle Value
0
1
2
...
ETV-1
ETV
PMW Waveform Duty Cycles
PWM Waveform =
#Clock Cycles
When Waveform is High
0
2
3
...
ETV
ETV+1
⎧
⎨
⎩
Table
high when TC DCV and DCV 0
low when DCV
24-2.
≤
=
0 or TC DCV
#Clock Cycles
When Waveform is Low
ETV+1
ETV-1
ETV-2
...
1
0
>
≠
Figure 24-3 on page 551
AT32UC3L
550