AT32UC3L064_1 ATMEL [ATMEL Corporation], AT32UC3L064_1 Datasheet - Page 549

• Manufacturer Part Number: AT32UC3L064_1
• Description: AVR32 32-bit Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

24.6.3
24.6.3.1
32099A–AVR32–06/09
Spread Spectrum Counter
Special considerations
zero). When the timebase counter reaches its effective top value, it restarts counting from zero.
The period of the PWMA output waveform is then:
The timebase counter can be reset by writing a one to the Timebase Clear bit in CR (CR.TCLR).
Note that this can cause a glitch to the output PWM waveforms in use.
The spread spectrum counter allows the generation of constantly varying duty cycles on the out-
put PWM waveforms. This is achieved by varying the effective top value of the timebase counter
in a range defined by the spread spectrum counter value.
When CR.SPREAD is not zero, the spread spectrum counter is enabled. Its range is defined by
CR.SPREAD. It starts to count from -CR.SPREAD when the PWMA is enabled or after reset
and counts upwards. When it reaches CR.SPREAD, it restarts to count from -CR.SPREAD
again. The spread spectrum counter will cause the effective top value (ETV) to vary from TOP-
SPREAD to TOP+SPREAD.
varying duty cycle on the PWM output waveforms though the duty cycle values stored are
unchanged.
Figure 24-2. PWMA Adjusting Top Value for Timebase Counter
The maximum value of the timebase counter is 255. If SPREAD is written to a value that will
cause the ETV to exceed this value, the spread spectrum counter’s range will be limited to pre-
vent the timebase counter to exceed its maximum value.
If SPREAD is written to a value causing (TOP-SPREAD) to be below zero, the spread specturm
counter’s range will be limited to prevent the timebase counter to count below zero.
In both cases, the SPREAD value read from the Control Register will be the same value as writ-
ten to the SPREAD field.
0xFF
0x0
Duty Cycle
SPREAD
TOP
-SPREAD
Figure 24-2 on page 549
T
PWMA
=
(
ETV
+
Adjusting top value range
for the timerbase counter
1
) T
illustrates this. This leads to a constantly
⋅
GCLK
AT32UC3L
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