AT32UC3L064_1 ATMEL [ATMEL Corporation], AT32UC3L064_1 Datasheet - Page 416

• Manufacturer Part Number: AT32UC3L064_1
• Description: AVR32 32-bit Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

20.7.10
20.7.10.1
Figure 20-39. Master Node with PDCA (PDCM=1)
32099A–AVR32–06/09
WRITE BUFFER
IDENTIFIER
CHKTYP
CHKDIS
PARDIS
DATA N
DATA 0
FSDIS
NACT
DLM
DLC
|
|
|
|
LIN Frame Handling With The Peripheral DMA Controller
Master Node Configuration
PDCA
(DMA)
The USART can be used in association with the Peripheral DMA Controller (PDCA) in order to
transfer data directly into/from the on- and off-chip memories without any processor intervention.
The PDCA uses the trigger flags, TXRDY and RXRDY, to write or read into the USART. The
PDCA always writes in the Transmit Holding register (THR) and it always reads in the Receive
Holding register (RHR). The size of the data written or read by the PDCA in the USART is always
a byte.
The user can choose between two PDCA modes by the PDCM bit in the LIN Mode register
(LINMR):
The WRITE buffer also contains the Identifier and the DATA, if the USART sends the response
(NACT = PUBLISH).
The READ buffer contains the DATA if the USART receives the response (NACT =
SUBSCRIBE).
• PDCM = 1: the LIN configuration is stored in the WRITE buffer and it is written by the PDCA
• PDCM = 0: the LIN configuration is not stored in the WRITE buffer and it must be written by
in the Transmit Holding register THR (instead of the LIN Mode register LINMR). Because the
PDCA transfer size is limited to a byte, the transfer is split into two accesses. During the first
access the bits, NACT, PARDIS, CHKDIS, CHKTYP, DLM and FDIS are written. During the
second access the 8-bit DLC field is written.
the user in the LIN Mode register (LINMR).
Peripheral
RXRDY
bus
NODE ACTION = PUBLISH
LIN CONTROLLER
USART3
WRITE BUFFER
READ BUFFER
IDENTIFIER
CHKTYP
CHKDIS
PARDIS
DATA N
DATA 0
FSDIS
NACT
DLM
DLC
|
|
|
|
(DMA)
PDCA
Peripheral
RXRDY
TXRDY
bus
NODE ACTION = SUBSCRIBE
AT32UC3L
LIN CONTROLLER
USART3
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