AT32UC3L064_1 ATMEL [ATMEL Corporation], AT32UC3L064_1 Datasheet - Page 337

• Manufacturer Part Number: AT32UC3L064_1
• Description: AVR32 32-bit Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

19.6.2.4
19.6.2.5
19.6.2.6
19.6.2.7
32099A–AVR32–06/09
Pin Output Driver Control
Open Drain Mode
Each GPIO pin can be independently configured to operate in Open Drain mode. This permits several drivers
to be connected on the same GPIO pin. The drivers should only actively drive the pin low. An external pull-up
resistor (or enabling the internal one) is generally required to guarantee a high level on the pin when no driver
is active. The Open Drain mode is controlled by the Open Drain Mode Enable Register (ODMER)Input
Schmitt Trigger
Interrupts
Figure 19-3. Output Pin Timings
The GPIO has registers for controlling output drive properties of each pin, such as output driving
capability and slew rate control.
The driving capability is controlled by the Output Driving Capability Registers (ODCRn) and the
slew rate settings are controlled by the Output Slew Rate Registers (OSRRn).
For a GPIO pin with four different slew rate settings, a slew rate of two can be selected by writing
a zero to the OSRR0 register at the bit position corresponding to the GPIO pin, and a one to the
OSRR1 at the same bit position. The ODCRn registers are configured in the same way.
Each GPIO pin can be configured with an input Schmitt trigger. An input Schmitt trigger filters
input signal using an hysteresis function, stopping noise from propagation into the system. The
input Schmitt trigger can be enabled and disabled by writing a one and a zero respectively to the
Schmitt Trigger Enable Register (STER).
The GPIO can be configured to generate an interrupt when it detects a change on a GPIO pin.
Interrupts on a pin are enabled by writing a one to the corresponding bit in the Interrupt Enable
Register (IER). The module can be configured to generate an interrupt whenever a pin changes
value, or only on rising or falling edges. This is controlled by the Interrupt Mode Registers
(IMRn). Interrupts on a pin can be enabled regardless of the GPIO pin being controlled by the
GPIO or assigned to a peripheral function.
An interrupt can be generated on each GPIO pin. These interrupt generators are further grouped
into groups of eight and connected to the interrupt controller. An interrupt request from any of the
GPIO pin generators in the group will result in an interrupt request from that group to the inter-
rupt controller if the corresponding bit for the GPIO pin in the IER is set. By grouping interrupt
generators into groups of eight, four different interrupt handlers can be installed for each GPIO
port.
Write OVR to 1
Write OVR to 0
OVR / I/O Line
CLK_GPIO
PVR
PB Access
PB Access
AT32UC3L
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