AT32UC3L064_1 ATMEL [ATMEL Corporation], AT32UC3L064_1 Datasheet - Page 196

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AT32UC3L064_1

Manufacturer Part Number
AT32UC3L064_1
Description
AVR32 32-bit Microcontroller
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
14.5.4
14.5.4.1
14.5.4.2
32099A–AVR32–06/09
Generic clocks
Enabling a generic clock
Disabling a generic clock
that the DFLL0RDY bit in PCLKSR register is high before writing. A write to a configuration reg-
ister while DFLL0RDY is low will be ignored.
Timers, communication modules, and other modules connected to external circuitry may require
specific clock frequencies to operate correctly. The SCIF contains an implementation defined
number of generic clocks that can provide a wide range of accurate clock frequencies.
Each generic clock module runs from either clock source listed in the table on
page
clock can be independently enabled and disabled, and is also automatically disabled along with
peripheral clocks by the Sleep Controller in the Power Manager.
Figure 14-6. Generic clock generation
A generic clock is enabled by writing the CEN bit in GCCTRL to one. Each generic clock can
individually select a clock source by setting the OSCSEL bits. The source clock can optionally be
divided by writing DIVEN to one and the division factor to DIV, resulting in the output frequency:
The generic clock can be disabled by writing CEN to zero or entering a sleep mode that disables
the PB clocks. In either case, the generic clock will be switched off on the first falling edge after
the disabling event, to ensure that no glitches occur. If CEN is written to zero, the bit will still read
as one until the next falling edge occurs, and the clock is actually switched off. When writing
CEN to zero, the other bits in GCCTRL should not be changed until CEN reads as zero, to avoid
glitches on the generic clock.
When the clock is disabled, both the prescaler and output are reset.
234. The selected source can optionally be divided by any even integer up to 512. Each
f
GCLK
= f
SRC
OSCSEL
/
(2*(DIV+1))
Divider
DIV
DIVEN
0
1
Sleep Controller
Mask
CEN
AT32UC3L
Generic Clock
Table 14-9 on
196

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