AT32UC3L064_1 ATMEL [ATMEL Corporation], AT32UC3L064_1 Datasheet - Page 523

• Manufacturer Part Number: AT32UC3L064_1
• Description: AVR32 32-bit Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

Figure 23-8. Master Write with Multiple Data Bytes
23.8.4
32099A–AVR32–06/09
TCOMP
TXRDY
TWD
Write THR (Data n)
NBYTES set to m
Slave Receiver Mode
S
DADR
The TWI transfers require the receiver to acknowledge each received data byte. During the
acknowledge clock pulse (9th pulse), the slave releases the data line (HIGH), enabling the
master to pull it down in order to generate the acknowledge. The slave polls the data line dur-
ing this clock pulse and sets the Not Acknowledge bit (NAK) in the Status Register if the
master does not acknowledge the data byte. A NAK means that the master does not wish to
receive additional data bytes. As with the other status bits, an interrupt can be generated if
enabled in the Interrupt Enable Register (IER).
TXRDY is used as Transmit Ready for the Peripheral DMA Controller transmit channel.
The end of the complete transfer is marked by the SR.TCOMP bit set to one. See
on page 523
Figure 23-7. Slave Transmitter with One Data Byte
If TWIS matches an address in which the R/W bit in the TWI address phase transfer is
cleared, it will enter slave receiver mode and clear SR.TRA.
After the address phase, the following is repeated:
7. If REPEATED START is received, SR.REP will be set.
1. If SMBus mode and PEC is used, NBYTES must be set up with the number of bytes
2. Receive a byte. Set SR.BTF when done.
W
to receive. This is necessary in order to know which of the received bytes is the PEC
byte. NBYTES can also be used to count the number of bytes received if using DMA.
TCOMP
TXRDY
A
TWD
and
Write THR (DATA)
NBYTES set to 1
S
Write THR (Data n+1)
DATA n
Figure 23-8 on page
DADR
A
W
523.
Write THR (Data n+m)
DATA n+5
A
Last data sent
DATA
A
(ACK received and NBYTES= 0)
DATA n+m
A
(ACK received and NBYTES= 0)
STOP sent automatically
STOP sent automatically
P
AT32UC3L
A
P
Figure 23-7
523