MC9S12DG256C FREESCALE [Freescale Semiconductor, Inc], MC9S12DG256C Datasheet - Page 108

• Manufacturer Part Number: MC9S12DG256C
• Description: device made up of standard HCS12 blocks and the HCS12 processor core
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

MC9S12DP256B Device User Guide — V02.15
The loop bandwidth f
typical values are 50. = 0.9 ensures a good transient response.
And finally the frequency relationship is defined as
With the above inputs the resistance can be calculated as:
The capacitance C
The capacitance C
The stabilization delays shown in Table A-16 are dependant on PLL operational settings and external
component selection (e.g. crystal, XFC filter).
A.5.3.2 Jitter Information
The basic functionality of the PLL is shown in Figure A-2. With each transition of the clock f
deviation from the reference clock f
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-3.
110
s
p
can now be calculated as:
should be chosen in the range of:
C
f
C
should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
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C
2
For More Information On This Product,
s
+
n
ref
=
=
is measured and input voltage to the VCO is adjusted
C
1
--------------------- -
f
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ref
s
f
------------ -
2
+
R
VCO
f
f
ref
C
20 C
=
2
2
R
2
---------------------------- -
=
----- -
50
1
2
p
0.516
-------------- -
f
K
C
n f
C
f
synr
C
R
s
<
C
;
10
------------- -
4 50
+
f
=
ref
1
0.9
;
=
0.9
cmp
, the