HYB18T512400AC Infineon Technologies AG, HYB18T512400AC Datasheet - Page 15

• Manufacturer Part Number: HYB18T512400AC
• Description: DDR2 Registered Memory Modules
• Manufacturer: Infineon Technologies AG

4.5 I
(V
Data Sheet
Preliminary
Notes:
1. IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.
2. Definitions for IDD:
3. IDD1, IDD4R, and IDD7 current measurements are defined with the outputs disabled (Iout = 0 mA). To achieve this on module
3. For two rank modules: For all active current measurements the other rank is in Precharge Power-Down Mode IDD2P
4. RESET signal is high for all currents, except for IDD6 “Self Refresh”.
5. All current measurements includes Register and PLL current consumption.
Symbol
I
I
DD
I
DD3P(0)
DD3P(1)
I
I
I
I
I
I
I
I
I
DD4W
I
I
level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
DD2N
DD2Q
DD3N
DD4R
DD5D
DD2P
DD5B
DD0
DD1
DD6
DD7
DD
= 1.8V
Measurement Conditions
Operating Current - One bank Active - Precharge
t
inputs are SWITCHING, Databus inputs are SWITCHING.
Operating Current - One bank Active - Read - Precharge
IOUT = 0 mA, BL = 4, t
CKE is HIGH, CS is high between valid commands. Address and control inputs are SWITCHING, Databus inputs are
SWITCHING.
Precharge Power-Down Current: All banks idle; CKE is LOW; t
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
Precharge Standby Current: All banks idle; CS is HIGH
Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Precharge Quiet Standby Current: All banks idle; CS is HIGH; CKE is HIGH; t
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
Active Power-Down Current: All banks open; t
inputs are FLOATING.
Active Power-Down Current: All banks open; t
inputs are FLOATING.
Active Standby Current: All banks open; t
valid commands.
Operating Current - Burst Read: All banks open; Continuous burst reads; BL = 4;
tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands.
Address inputs are SWITCHING; Data Bus inputs are SWITCHING;
Operating Current - Burst Write: All banks open; Continuous burst writes; BL = 4;
tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands.
Address inputs are SWITCHING; Data Bus inputs are SWITCHING;
Burst Auto-Refresh Current: t
between valid commands,
Distributed Auto-Refresh Current: t
between valid commands,
Self-Refresh Current: CKE
inputs are FLOATING. RESET = Low. IDD6 current values are guaranteed up to TCASE of 85oC max.
All Bank Interleave Read Current:
1. All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address
2. Timing pattern:
3. Legend: A = Activate, RA = Read with Auto-Precharge, D=DESELECT
LOW is defined as VIN <= VIL(ac)max; HIGH is defined as VIN >= VIH(ac)min.
STABLE is defined as inputs are stable at a HIGH or LOW level.
FLOATING is defined as inputs are VREF = VDDQ / 2.
SWITCHING is defined as:
inputs are changing between HIGH and LOW every other clock (once per two cycles) for address and control signals, and
inputs changing between HIGH and LOW every other clock (once per cycle) for DQ signals not including mask or strobes.
CK
bus inputs are STABLE during DESELECTS. Iout = 0mA.
= t
0.1V; V
CKmin.
- DDR2 -400 : A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D
- DDR2 -533 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
- DDR2 -667 : A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D
, t
DDQ
RC
= t
Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
MRS A12 bit is set to “0” (Fast Power-down Exit);
MRS A12 bit is set to “1” (Slow Power-down Exit);
= 1.8V
RCmin.,
CK
= t
Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
tRAS = tRASmin., CKE is HIGH, CS is high between valid commands. Address and control
CKmin., tRC = tRCmin., tRAS = tRASmin.,tRCD = tRCDmin.,AL = 0, CL = CLmin.;
0.1V)
0.2V; external clock off, CK and CK at 0V;
CK
= t
CKmin.,
CK
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
= t
CK
CKmin.,
Refresh command every t
= t
CK
CK
CKmin.;
Parameter/Condition
Refresh command every t
= t
= t
15
CKmin.,
CKmin.,
I
OUT
t
RAS
;
Registered DDR2 SDRAM Modules
CKE is HIGH; t
= 0mA.
CKE is LOW;
CKE is LOW;
= t
RASmax
CK
= t
RFC
; tRP = tRPmin.,CKE is HIGH; CS is high between
CKmin.;
Other control and address inputs are FLOATING, Data bus
CK
= t
Other control and address inputs are STABLE, Data bus
Other control and address inputs are STABLE, Data bus
RFC
= t
RFCmin. interval, CKE is HIGH,
CKmin.;
CK
= t
= t
AL = 0, CL = CLmin.;
REFI interval, CKE is LOW and
AL = 0, CL = CLmin.;
CKmin.;
Rev. 0.85, 2004-04
t
CK
t
CK
CS is HIGH
= t
= t
CKmin.;
CKmin.;
CS is HIGH