HYB18T512400AC Infineon Technologies AG, HYB18T512400AC Datasheet - Page 18

• Manufacturer Part Number: HYB18T512400AC
• Description: DDR2 Registered Memory Modules
• Manufacturer: Infineon Technologies AG

5.2 ODT AC Electrical Characteristics and Operating Conditions (all speed bins)
Data Sheet
Preliminary
1. For details and notes see the relevant INFINEON component datasheet
2. Timing definition and values for tis, tih, tds and tdh may change due to actual JEDEC work. This may also effect the SPD code
Symbol Parameter / Condition
Symbol
t
t
t
t
t
t
t
AONPD
AOFPD
t
for these parameters.
t
XARDS
t
t
AOND
t
AOFD
t
ANPD
DELAY
AXPD
t
t
t
t
t
t
t
t
XARD
XSRD
XSNR
AON
t
t
AOF
WTR
REFI
RCD
t
RRD
CCD
t
DAL
RTP
CKE
WR
OIT
RP
XP
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down Modes)
ODT turn-off delay
ODT turn-off
ODT turn-off delay (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
Active to Read or Write delay (with and without Auto-Pre-
charge) delay
Precharge command period
Active bank A to Active bank
B command
CAS A to CAS B Command Period
Write recovery time
Auto precharge write recovery + precharge time
Internal write to read command delay
Internal read to precharge command delay
Exit power down to any valid command
(other than NOP or Deselect)
Exit active power-down mode to read command
(slew exit, lower power)
Exit precharge power-down to any valid command (other
than NOP or Deselect)
Exit Self-Refresh to read command
Exit Self-Refresh to non-read command
CKE minimum high and low pulse width
OCD drive mode output delay
Minimum time clocks remain ON after CKE asynchro-
nously drops low
Average Periodic Refresh
Interval
Parameter
DDR2-400/533
DDR2-667
(1k page size)
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
85
0
o
x4 & x8
o
C - 85
C - 95
o
o
C
C
18
tAC(min) + 2 ns
tAC(min) + 2 ns
Registered DDR2 SDRAM Modules
tAC(min)
tAC(min)
tAC(min)
tRFC + 10
WR+tRP
min.
tIS+tCK
2.5
6 - AL
2
3
8
Min
+tIH
200
7.5
7.5
15
15
15
10
2
2
2
3
0
-
-
DDR2-400
-5
Max
7.8
3.9
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.5 t
2 t
tAC(max) + 0.7 ns
CK +
tAC(max) + 0.6 ns
tAC(max) + 1 ns
CK +
tRFC + 10
tAC(max) + 1 ns
WR+tRP
tIS+tCK
tAC(max) + 1 ns
6 - AL
max.
+tIH
Min
200
7.5
7.5
7.5
2.5
15
15
15
2
2
2
3
0
2
-
-
-
-
DDR2-533
Rev. 0.85, 2004-04
-3.7
Max
7.8
3.9
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Units
t
t
t
t
ns
ns
ns
ns
CK
CK
CK
CK
Unit
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
CK
CK
CK
CK
CK
CK
CK